(no commit message)
authorcolepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Sun, 22 Nov 2020 20:20:58 +0000 (20:20 +0000)
committerIkiWiki <ikiwiki.info>
Sun, 22 Nov 2020 20:20:58 +0000 (20:20 +0000)
HDL_workflow/ECP5_FPGA.mdwn

index 1cdd0e7e2fb908cfa9c3cc632839db930e99fc77..11134812a36b0933bd559c8427d09ff1bd228719 100644 (file)
@@ -191,9 +191,8 @@ Table of connections:
 
 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 |-------------|-------------|----------------|-----------|
-|1 GND        | GND         | 4 (GND)        |   Black   |
-|2 NC         | NC          |  NC            |    NC     |
 |39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
+|1 GND        | GND         | 4 (GND)        |   Black   |
 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 |6 IO31       |  B9         |    9 (TCK)     |   White   |