out-of-order execution, although it is strongly recommended to add
predication capability directly into SIMD backend units.
-In Power ISA v3.0B pseudo-code form, an ADD operation, assuming both
-source and destination have been "tagged" as Vectors, is simply:
+A typical Cray-style Scalable Vector ISA (where a SIMD one has a fixed
+non-negotiable static parameter instead of a runtime-dynamic VL)
+performs its arithmetic as:
+
+ for i = 0 to VL-1:
+ VPR(RT)[i] = VPR[RA][i] + VPR(RB)[i]
+
+In Power ISA v3.0B pseudo-code form, an ADD operation in Simple-V,
+assuming both source and destination have been "tagged" as Vectors,
+is simply:
for i = 0 to VL-1:
GPR(RT+i) = GPR(RA+i) + GPR(RB+i)