(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index e0b3bc63c891bf359123adf29b5669d6b13d1cc1..aed1adabcaf195ec2ec659fe6e664340c0342d38 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -7,7 +7,7 @@ SVP64 is designed around these fundamental and inviolate principles:
 1. There are no actual Vector instructions: Scalar instructions
    are the sole exclusive bedrock.
 2. No scalar instruction ever deviates in its encoding or meaning
-   just because it is prefixed (caveats below)
+   just because it is prefixed (semantic caveats below)
 3. A hardware-level for-loop makes vector elements 100% synonymous
    with scalar instructions (the suffix)
 
@@ -22,15 +22,17 @@ There are a few exceptional places where these rules get
 bent, and others where the rules take some explaining,
 and this page tracks them.
 
-The modification caveat obviously exempts element width overrides,
+The modification caveat in (2) above semantically
+exempts element width overrides,
 which still do not actually modify the meaning of the instruction:
-an add remains an add, even if it is only an 8-bit add rather than
-a 64-bit add. elwidth overrides *definitely* do not alter the 3.0 encoding.
+an add remains an add, even if its override makes it an 8-bit add rather than
+a 64-bit add. elwidth overrides *definitely* do not alter the actual
+Scalar v3.0 ISA encoding itself.
 Other "modifications" such as saturation or Data-dependent Fail-First
 likewise are post-augmentation or post-analysis, and do not actually
 fundamentally change an add operation into a subtract for example.
 
-An experiment was attempted to modify LD-immediate instructions
+*(An experiment was attempted to modify LD-immediate instructions
 to include a
 third RC register i.e. reinterpret the normal
 v3.0 32-bit instruction as a
@@ -41,7 +43,7 @@ hard way: it is infinitely preferable to add a 32-bit Scalar Load-with-Shift
 instruction *first*, which then inherently becomes Vectorised.
 Perhaps a future Power ISA spec will have this Load-with-Shift instruction:
 both ARM and x86 have it, because it saves greatly on instruction count in
-hot-loops. 
+hot-loops.)*
 
 # Instruction Groups