+++ /dev/null
-# Tuesday 7th Nov
-
-TODO: Finish filling up from notes
-
-* Previous weeks' notes: NA
-* Next weeks' notes: [[meetings/sync_up/2023-11-14_15]]
-
-## Sadoon
-
--
-
-## Jacob
-
-- Made necessary fixes to pseudo-code to get a whole bunch of simulator
-tests working. [bug #1177](https://bugs.libre-soc.org/show_bug.cgi?id=1177)
-- Quoting Jacob:
- - "yeah, i made the changes since coping all insn inputs made TRAP
- not quite work since it modifies the SRR0/1 in self.spr instead of
- the locals in the compiled pseudo-code
- otherwise i'd have to change the parser to feed all locals into TRAP"
-
-## Andrey
-
-# Wednesday 8th November
-
-## Cesar
-
-- nextpnr-xilinx has issues with 2.5V I/O.
- - FPGA split I/O split into banks, each bank has its own voltage.
- - For now ignore switches/LEDs, test UART as it's at 3.3V
-(and that's enough for Libre-SOC).
- - Need to make a bug report in upstream nextpnr-xilinx.
-
-- LD/ST CompUnit (CU) formal verification:
- - During test, CompUnit communicates with scoreboard and registerfiles.
- - Issue instruction to CU, fetch operands, store in reg's, send to ALU,
-store result to regfile.
- - Put counters for those tests. Counter values must match
-(fetch reg's only once, read ALU only *after* operands have been written).
-
-- FOSDEM:
- - Suggested people to invite:
- - [Matt Venn](https://www.mattvenn.net/)
-([Zero to ASIC](https://www.zerotoasiccourse.com/) course author)
- - Mohamed Kassem ([e-fabless](https://efabless.com/))
- - Shouldn't make all about LibreSOC (since we were lucky to get a devroom,
-should also make the space available to other projects in the same area).
-
-[[!tag meeting2023]]
-[[!tag meeting_sync_up]]
+++ /dev/null
-# Tuesday 14th November
-
-* Previous weeks' notes: [[meetings/sync_up/2023-11-07_08]]
-* Next weeks' notes: [[meetings/sync_up/2023-11-21_22]]
-
-## Sadoon
-
-- Planning to start making snippets of Poly-1305, asked for advice on
-how to setup test file (examples
-
-## Jacob
-
-- Created budget estimates for
-[bug #1169](https://bugs.libre-soc.org/show_bug.cgi?id=1169).
-Asked for approval whether can proceed or not.
-
-- Asked for the reason of the budget distribution in
-[bug #983](https://bugs.libre-soc.org/show_bug.cgi?id=983)
-(This bug's budget will be used to fund bug #1169.)
-
-## Andrey
-
-- Luke and I in conversation with Michiel to query about FOSDEM costs.
-Later this week on another call to finalise the ongoing grant MoU.
-*(The MoU was signed the following week.)*
-
-- Continued to work on Libre-SOC documentation included in [[HDL_workflow]]
-and [[HDL_workflow/libresoc_bug_process]]. See
-[bug #1126](https://bugs.libre-soc.org/show_bug.cgi?id=1126) for updates.
-
-- Looked at list of tasks under bug #1169 and gave Jacob the go-ahead
-to proceed with tasks that are definitely required, and wait for Luke's
-response on the rest.
-*(Given my lack of understanding and background, this was a mistake, and
-I should have waited for Luke's comments on the task list. This is noted
-for future bugs.)*
-
-# Wednesday 15th November
-
-## Cesar
-
-- Working through the formal correctness proof for the ld/st unit.
- - Says will be similar to compunit.
- - Need to fetch operands, store results.
-- There are 2 compunits in two files:
- - ALU Compunit does everything but ld/st.
- - LD/ST Compunit is for mem-reg/reg-mem.
-(Only the ld/st proof is covered by current grant, see
-[bug #1036](https://bugs.libre-soc.org/show_bug.cgi?id=1036))
-
-On future grant:
-
-- Make sure future grants include budget for formal verification.
-
-When doing HDL design:
-
-- Ideally should be able to switch between *design, verification, simulation.*
-
-On Fosdem:
-
-- What to do about talk submissions which use the unauthorised for of nMigen?...
-
-
-[[!tag meeting2023]]
-[[!tag meeting_sync_up]]
--- /dev/null
+# Tuesday 7th Nov
+
+TODO: Finish filling up from notes
+
+* Previous weeks' notes: NA
+* Next weeks' notes: [[meetings/sync_up/2023-11-14_15]]
+
+## Sadoon
+
+-
+
+## Jacob
+
+- Made necessary fixes to pseudo-code to get a whole bunch of simulator
+tests working. [bug #1177](https://bugs.libre-soc.org/show_bug.cgi?id=1177)
+- Quoting Jacob:
+ - "yeah, i made the changes since coping all insn inputs made TRAP
+ not quite work since it modifies the SRR0/1 in self.spr instead of
+ the locals in the compiled pseudo-code
+ otherwise i'd have to change the parser to feed all locals into TRAP"
+
+## Andrey
+
+# Wednesday 8th November
+
+## Cesar
+
+- nextpnr-xilinx has issues with 2.5V I/O.
+ - FPGA split I/O split into banks, each bank has its own voltage.
+ - For now ignore switches/LEDs, test UART as it's at 3.3V
+(and that's enough for Libre-SOC).
+ - Need to make a bug report in upstream nextpnr-xilinx.
+
+- LD/ST CompUnit (CU) formal verification:
+ - During test, CompUnit communicates with scoreboard and registerfiles.
+ - Issue instruction to CU, fetch operands, store in reg's, send to ALU,
+store result to regfile.
+ - Put counters for those tests. Counter values must match
+(fetch reg's only once, read ALU only *after* operands have been written).
+
+- FOSDEM:
+ - Suggested people to invite:
+ - [Matt Venn](https://www.mattvenn.net/)
+([Zero to ASIC](https://www.zerotoasiccourse.com/) course author)
+ - Mohamed Kassem ([e-fabless](https://efabless.com/))
+ - Shouldn't make all about LibreSOC (since we were lucky to get a devroom,
+should also make the space available to other projects in the same area).
+
+[[!tag meeting2023]]
+[[!tag meeting_sync_up]]
--- /dev/null
+# Tuesday 14th November
+
+* Previous weeks' notes: [[meetings/sync_up/2023-11-07_08]]
+* Next weeks' notes: [[meetings/sync_up/2023-11-21_22]]
+
+## Sadoon
+
+- Planning to start making snippets of Poly-1305, asked for advice on
+how to setup test file (examples
+
+## Jacob
+
+- Created budget estimates for
+[bug #1169](https://bugs.libre-soc.org/show_bug.cgi?id=1169).
+Asked for approval whether can proceed or not.
+
+- Asked for the reason of the budget distribution in
+[bug #983](https://bugs.libre-soc.org/show_bug.cgi?id=983)
+(This bug's budget will be used to fund bug #1169.)
+
+## Andrey
+
+- Luke and I in conversation with Michiel to query about FOSDEM costs.
+Later this week on another call to finalise the ongoing grant MoU.
+*(The MoU was signed the following week.)*
+
+- Continued to work on Libre-SOC documentation included in [[HDL_workflow]]
+and [[HDL_workflow/libresoc_bug_process]]. See
+[bug #1126](https://bugs.libre-soc.org/show_bug.cgi?id=1126) for updates.
+
+- Looked at list of tasks under bug #1169 and gave Jacob the go-ahead
+to proceed with tasks that are definitely required, and wait for Luke's
+response on the rest.
+*(Given my lack of understanding and background, this was a mistake, and
+I should have waited for Luke's comments on the task list. This is noted
+for future bugs.)*
+
+# Wednesday 15th November
+
+## Cesar
+
+- Working through the formal correctness proof for the ld/st unit.
+ - Says will be similar to compunit.
+ - Need to fetch operands, store results.
+- There are 2 compunits in two files:
+ - ALU Compunit does everything but ld/st.
+ - LD/ST Compunit is for mem-reg/reg-mem.
+(Only the ld/st proof is covered by current grant, see
+[bug #1036](https://bugs.libre-soc.org/show_bug.cgi?id=1036))
+
+On future grant:
+
+- Make sure future grants include budget for formal verification.
+
+When doing HDL design:
+
+- Ideally should be able to switch between *design, verification, simulation.*
+
+On Fosdem:
+
+- What to do about talk submissions which use the unauthorised for of nMigen?...
+
+
+[[!tag meeting2023]]
+[[!tag meeting_sync_up]]
--- /dev/null
+# Tuesday 14th November
+
+* Previous weeks' notes: [[meetings/sync_up/2023-11-07_08]]
+* Next weeks' notes: [[meetings/sync_up/2023-11-21_22]]
+
+## Sadoon
+
+- Planning to start making snippets of Poly-1305, asked for advice on
+how to setup test file (examples
+
+## Jacob
+
+- Created budget estimates for
+[bug #1169](https://bugs.libre-soc.org/show_bug.cgi?id=1169).
+Asked for approval whether can proceed or not.
+
+- Asked for the reason of the budget distribution in
+[bug #983](https://bugs.libre-soc.org/show_bug.cgi?id=983)
+(This bug's budget will be used to fund bug #1169.)
+
+## Andrey
+
+- Luke and I in conversation with Michiel to query about FOSDEM costs.
+Later this week on another call to finalise the ongoing grant MoU.
+*(The MoU was signed the following week.)*
+
+- Continued to work on Libre-SOC documentation included in [[HDL_workflow]]
+and [[HDL_workflow/libresoc_bug_process]]. See
+[bug #1126](https://bugs.libre-soc.org/show_bug.cgi?id=1126) for updates.
+
+- Looked at list of tasks under bug #1169 and gave Jacob the go-ahead
+to proceed with tasks that are definitely required, and wait for Luke's
+response on the rest.
+*(Given my lack of understanding and background, this was a mistake, and
+I should have waited for Luke's comments on the task list. This is noted
+for future bugs.)*
+
+# Wednesday 15th November
+
+## Cesar
+
+- Working through the formal correctness proof for the ld/st unit.
+ - Says will be similar to compunit.
+ - Need to fetch operands, store results.
+- There are 2 compunits in two files:
+ - ALU Compunit does everything but ld/st.
+ - LD/ST Compunit is for mem-reg/reg-mem.
+(Only the ld/st proof is covered by current grant, see
+[bug #1036](https://bugs.libre-soc.org/show_bug.cgi?id=1036))
+
+On future grant:
+
+- Make sure future grants include budget for formal verification.
+
+When doing HDL design:
+
+- Ideally should be able to switch between *design, verification, simulation.*
+
+On Fosdem:
+
+- What to do about talk submissions which use the unauthorised for of nMigen?...
+
+
+[[!tag meeting2023]]
+[[!tag meeting_sync_up]]
projects / libreriscv.git / commitdiff