soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters...

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index e872df1333d19779c34eeeacc6ef2becdefc25df..4d27995b4bd0abf9c7a5b6113e390796b27f9cd4 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -57,7 +57,7 @@ class LM32(Module):
 
         i_adr_o = Signal(32)
         d_adr_o = Signal(32)
-        self.specials += Instance("lm32_cpu",
+        self.cpu_params = dict(
             p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
 
             i_clk_i=ClockSignal(),
@@ -131,3 +131,6 @@ class LM32(Module):
             platform.add_verilog_include_path(os.path.join(vdir, "config"))
         else:
             raise TypeError("Unknown variant {}".format(variant))
+
+    def do_finalize(self):
+        self.specials += Instance("lm32_cpu", **self.cpu_params)

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 05007cf5152422115109b7a5fc79ca6666260f74..742760ccacb8a36e43bbae7e5c4211acb33d99c3 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -50,7 +50,7 @@ class Minerva(Module):
 
         # # #
 
-        self.specials += Instance("minerva_cpu",
+        self.cpu_params = dict(
             # clock / reset
             i_clk=ClockSignal(),
             i_rst=ResetSignal(),
@@ -93,3 +93,6 @@ class Minerva(Module):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, "minerva.v"))
+
+    def do_finalize(self):
+        self.specials += Instance("minerva_cpu", **self.cpu_params)

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 9a54d820f54cf1a05a9d6c49b7df2b86aab92582..56af64379edcd2a1c105a3ca21cb3ef0103ce2bc 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -96,14 +96,14 @@ class MOR1KX(Module):
         )
 
         if variant == "linux":
-            cpu_args.update(dict(
+            cpu_args.update(
                 # Linux needs the memory management units.
                 p_FEATURE_IMMU="ENABLED",
                 p_FEATURE_DMMU="ENABLED",
                 # FIXME: Currently we need the or1k timer when we should be
                 # using the litex timer.
                 p_FEATURE_TIMER="ENABLED",
-            ))
+            )
             # FIXME: Check if these are needed?
             use_defaults = (
                 "p_FEATURE_SYSCALL", "p_FEATURE_TRAP", "p_FEATURE_RANGE",
@@ -114,7 +114,7 @@ class MOR1KX(Module):
 
         i_adr_o = Signal(32)
         d_adr_o = Signal(32)
-        self.specials += Instance("mor1kx",
+        self.cpu_params = dict(
             **cpu_args,
 
             i_clk=ClockSignal(),
@@ -146,7 +146,8 @@ class MOR1KX(Module):
             i_dwbm_dat_i=d.dat_r,
             i_dwbm_ack_i=d.ack,
             i_dwbm_err_i=d.err,
-            i_dwbm_rty_i=0)
+            i_dwbm_rty_i=0
+        )
 
         self.comb += [
             self.ibus.adr.eq(i_adr_o[2:]),
@@ -163,3 +164,6 @@ class MOR1KX(Module):
             "verilog", "rtl", "verilog")
         platform.add_source_dir(vdir)
         platform.add_verilog_include_path(vdir)
+
+    def do_finalize(self):
+        self.specials += Instance("mor1kx", **self.cpu_params)

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 7a3c5600e93cc5719292ccb1c988c152e68d7422..0cf53523147e5559cc2b5ef9fe9c94262724cb7d 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -83,49 +83,46 @@ class PicoRV32(Module):
 
         # PicoRV32 parameters. To create a new variant, modify this dictionary
         # and change the desired parameters.
-        picorv32_params = {
-            "p_ENABLE_COUNTERS" : 1,
-            "p_ENABLE_COUNTERS64" : 1,
+        self.cpu_params = dict(
+            p_ENABLE_COUNTERS=1,
+            p_ENABLE_COUNTERS64=1,
             # Changing REGS has no effect as on FPGAs, the registers are
             # implemented using a register file stored in DPRAM.
-            "p_ENABLE_REGS_16_31" : 1,
-            "p_ENABLE_REGS_DUALPORT" : 1,
-            "p_LATCHED_MEM_RDATA" : 0,
-            "p_TWO_STAGE_SHIFT" : 1,
-            "p_TWO_CYCLE_COMPARE" : 0,
-            "p_TWO_CYCLE_ALU" : 0,
-            "p_CATCH_MISALIGN" : 1,
-            "p_CATCH_ILLINSN" : 1,
-            "p_ENABLE_PCPI" : 0,
-            "p_ENABLE_MUL" : 1,
-            "p_ENABLE_DIV" : 1,
-            "p_ENABLE_FAST_MUL" : 0,
-            "p_ENABLE_IRQ" : 1,
-            "p_ENABLE_IRQ_QREGS" : 1,
-            "p_ENABLE_IRQ_TIMER" : 1,
-            "p_ENABLE_TRACE" : 0,
-            "p_MASKED_IRQ" : 0x00000000,
-            "p_LATCHED_IRQ" : 0xffffffff,
-            "p_PROGADDR_RESET" : progaddr_reset,
-            "p_PROGADDR_IRQ" : progaddr_reset + 0x00000010,
-            "p_STACKADDR" : 0xffffffff
-        }
+            p_ENABLE_REGS_16_31=1,
+            p_ENABLE_REGS_DUALPORT=1,
+            p_LATCHED_MEM_RDATA=0,
+            p_TWO_STAGE_SHIFT=1,
+            p_TWO_CYCLE_COMPARE=0,
+            p_TWO_CYCLE_ALU=0,
+            p_CATCH_MISALIGN=1,
+            p_CATCH_ILLINSN=1,
+            p_ENABLE_PCPI=0,
+            p_ENABLE_MUL=1,
+            p_ENABLE_DIV=1,
+            p_ENABLE_FAST_MUL=0,
+            p_ENABLE_IRQ=1,
+            p_ENABLE_IRQ_QREGS=1,
+            p_ENABLE_IRQ_TIMER=1,
+            p_ENABLE_TRACE=0,
+            p_MASKED_IRQ=0x00000000,
+            p_LATCHED_IRQ=0xffffffff,
+            p_PROGADDR_RESET=progaddr_reset,
+            p_PROGADDR_IRQ=progaddr_reset + 0x00000010,
+            p_STACKADDR=0xffffffff
+        )
 
         if variant == "minimal":
-            picorv32_params.update({
-                "p_ENABLE_COUNTERS" : 0,
-                "p_ENABLE_COUNTERS64" : 0,
-                "p_TWO_STAGE_SHIFT" : 0,
-                "p_CATCH_MISALIGN" : 0,
-                "p_ENABLE_MUL" : 0,
-                "p_ENABLE_DIV" : 0,
-                "p_ENABLE_IRQ_TIMER" : 0
-            })
-
-        self.specials += Instance("picorv32",
-            # parameters dictionary
-            **picorv32_params,
-
+            self.cpu_params.update(
+                p_ENABLE_COUNTER=0,
+                p_ENABLE_COUNTERS64=0,
+                p_TWO_STAGE_SHIFT=0,
+                p_CATCH_MISALIGN=0,
+                p_ENABLE_MUL=0,
+                p_ENABLE_DIV=0,
+                p_ENABLE_IRQ_TIMER=0
+            )
+
+        self.cpu_params.update(
             # clock / reset
             i_clk=ClockSignal(),
             i_resetn=~(ResetSignal() | self.reset),
@@ -203,3 +200,6 @@ class PicoRV32(Module):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, "picorv32.v"))
+
+    def do_finalize(self):
+        self.specials += Instance("picorv32", **self.cpu_params)

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index dfea44a4c6a4458475245a331be5e7a6c5a53822..05f1927dd0b87dd2f110cbd0b642afc80295b70d 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -100,7 +100,7 @@ class RocketRV64(Module):
 
         # # #
 
-        self.specials += Instance("ExampleRocketSystem",
+        self.cpu_params += dict(
             # clock, reset
             i_clock=ClockSignal(),
             i_reset=ResetSignal() | self.reset,
@@ -246,3 +246,6 @@ class RocketRV64(Module):
             "AsyncResetReg.v",
             "EICG_wrapper.v",
         )
+
+    def do_finalize(self):
+        self.specials += Instance("ExampleRocketSystem", **self.cpu_params)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 0f9a2622cb62903cb8fb87f2486bffb28136d90f..747e0902162a6e7ad825f257390a286728913f3d 100644 (file)
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -50,7 +50,7 @@ class SERV(Module):
 
         # # #
 
-        self.specials += Instance("serv_top",
+        self.cpu_params -= dict(
             p_RESET_PC=cpu_reset_address,
 
             # clock / reset
@@ -91,3 +91,6 @@ class SERV(Module):
             "verilog", "rtl")
         platform.add_source_dir(vdir)
         platform.add_verilog_include_path(vdir)
+
+    def do_finalize(self):
+        self.specials += Instance("serv_top", **self.cpu_params)