static void
radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
{
- if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
+ if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
enum radv_cmd_flush_bits flags;
/* Force wait for graphics/compute engines to be idle. */
fprintf(f, "Enabled debug options: ");
- mask = device->debug_flags;
+ mask = device->instance->debug_flags;
while (mask) {
int i = u_bit_scan64(&mask);
fprintf(f, "%s, ", radv_get_debug_option_name(i));
device->instance = physical_device->instance;
device->physical_device = physical_device;
- device->debug_flags = device->instance->debug_flags;
-
device->ws = physical_device->ws;
if (pAllocator)
device->alloc = *pAllocator;
}
if (iview->image->cmask.size &&
- !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
+ !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
(pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
device->physical_device->rad_info.chip_class < VI ||
- create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC))
+ create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC))
surface->flags |= RADEON_SURF_DISABLE_DCC;
if (create_info->scanout)
surface->flags |= RADEON_SURF_SCANOUT;
} else {
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
- !(device->debug_flags & RADV_DEBUG_NO_HIZ)) {
+ !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
radv_image_alloc_htile(image);
image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
} else {
if (!iview->image->surface.htile_size)
return false;
- if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+ if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
return false;
if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
return false;
- if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+ if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
return false;
if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
pipeline->graphics.vtx_reuse_depth = 14;
}
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}
*pPipeline = radv_pipeline_to_handle(pipeline);
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}
return VK_SUCCESS;
/* We don't consider allocation failure fatal, we just start with a 0-sized
* cache. */
if (cache->hash_table == NULL ||
- (device->debug_flags & RADV_DEBUG_NO_CACHE))
+ (device->instance->debug_flags & RADV_DEBUG_NO_CACHE))
cache->table_size = 0;
else
memset(cache->hash_table, 0, byte_size);
struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
int queue_count[RADV_MAX_QUEUE_FAMILIES];
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
- uint64_t debug_flags;
bool llvm_supports_spill;
bool has_distributed_tess;
uint32_t *spirv = (uint32_t *) module->data;
assert(module->size % 4 == 0);
- if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
radv_print_spirv(spirv, module->size, stderr);
uint32_t num_spec_entries = 0;
nir_remove_dead_variables(nir, nir_var_local);
radv_optimize_nir(nir);
- if (device->debug_flags & RADV_DEBUG_DUMP_SHADERS)
+ if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
nir_print_shader(nir, stderr);
return nir;
unsigned *code_size_out)
{
enum radeon_family chip_family = device->physical_device->rad_info.family;
- bool dump_shaders = device->debug_flags & RADV_DEBUG_DUMP_SHADERS;
+ bool dump_shaders = device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS;
enum ac_target_machine_options tm_options = 0;
struct radv_shader_variant *variant;
struct ac_shader_binary binary;
if (key)
options.key = *key;
- options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
+ options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
options.supports_spill = device->llvm_supports_spill;
return shader_variant_create(device, module, shader, shader->stage,