i965: setup address rounding enable bits

The patch(based on the reading of the emulator) came from while I was
trying to fix the oglc pbo texImage.1PBODefaults fail. This case
generates a texture with the width and height equal to window's width
and height respectively, then try to texture it on the whole window.
So, it's exactly one texel for one pixel.  And, the min filter and mag
filter are GL_LINEAR. It runs with swrast OK, as expected. But it failed
with i965 driver.

Well, you can't tell the difference from the screen, as the error is
quite tiny. From my digging, it seems that there are some tiny error
happened while getting tex address. This will break the one texel for
one pixel rule in this case. Thus the linear result is taken, with tiny
error.

This patch would fix all oglc pbo subcase fail with the same issue on
both ILK, SNB and IVB.

v2: comments from Ian, make the address_round filed assignment consistent.
    (the sampler is alread memset to 0 by the xxx_update_samper_state
     caller, so need to assign 0 first)

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 308a842617e40efedb02d3ea66ab4e54530da074..5314ac6544d19a3064934b11b70fd56860f5f1f3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -196,6 +196,13 @@
 #define BRW_MIPFILTER_NEAREST     1   
 #define BRW_MIPFILTER_LINEAR      3
 
+#define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG      0x20
+#define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN      0x10
+#define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG      0x08
+#define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN      0x04
+#define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG      0x02
+#define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN      0x01
+
 #define BRW_POLYGON_FRONT_FACING     0
 #define BRW_POLYGON_BACK_FACING      1
 

diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 6834ebad78042c2fef33b4c136503201307b7f3c..8938561bf8ff2432ad3bfaff9ca618827fd6bcf2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -312,6 +312,15 @@ static void brw_update_sampler_state(struct brw_context *brw,
                              intel->batch.bo, brw->wm.sdc_offset[unit],
                              I915_GEM_DOMAIN_SAMPLER, 0);
    }
+
+   if (sampler->ss0.min_filter != BRW_MAPFILTER_NEAREST)
+      sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
+   if (sampler->ss0.mag_filter != BRW_MAPFILTER_NEAREST)
+      sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 }
 
 

diff --git a/src/mesa/drivers/dri/i965/gen7_sampler_state.c b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
index aee67c874729f9b646cb34cedde25c28320cb440..f6f51c54ac00396a3286a7b35fc5303a9cabe091 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
@@ -167,6 +167,15 @@ gen7_update_sampler_state(struct brw_context *brw, int unit,
    upload_default_color(brw, gl_sampler, unit);
 
    sampler->ss2.default_color_pointer = brw->wm.sdc_offset[unit] >> 5;
+
+   if (sampler->ss0.min_filter != BRW_MAPFILTER_NEAREST)
+      sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
+   if (sampler->ss0.mag_filter != BRW_MAPFILTER_NEAREST)
+      sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
+                                    BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 }