i965: Make brw_update_sampler_state use 8 bits for LOD fields on Gen7+.

This was the only actual difference between Gen4-6 and Gen7+ in terms of
the values we program.  The rest was just mechanical structure
rearrangement.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index b34e9f331d1d46475455b6e18fead0754ec3b59e..fbdb40e8fdf1a334c268e7f1cb392e13ec8f0f9d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -424,10 +424,11 @@ brw_update_sampler_state(struct brw_context *brw,
         intel_translate_shadow_compare_func(sampler->CompareFunc);
    }
 
-   const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), 6);
-   const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), 6);
+   const int lod_bits = brw->gen >= 7 ? 8 : 6;
+   const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), lod_bits);
+   const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), lod_bits);
    const int lod_bias =
-      S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), 6);
+      S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), lod_bits);
    const unsigned base_level = U_FIXED(0, 1);
 
    uint32_t border_color_offset;