+2002-02-07 Tom Rix <trix@redhat.com>
+
+ * config/rs6000/rs6000.c (reg_or_aligned_short_operand): New. For
+ immediates in ldu and stdu DS opcode field.
+ * config/rs6000/rs6000.md (movdi_update, movdi_update1): Use.
+ * config/rs6000/rs6000-protos.h: Add reg_or_aligned_short_operand.
+ * config/rs6000/rs6000.h (PREDICATE_CODES): Same.
+
2002-02-07 Jeff Sturm <jsturm@one-point.com>
* config/sparc/sparc.c (compute_frame_size): Don't correct frame
extern int cc_reg_not_cr0_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_short_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_neg_short_operand PARAMS ((rtx, enum machine_mode));
+extern int reg_or_aligned_short_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_u_short_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode));
extern int reg_or_arith_cint_operand PARAMS ((rtx, enum machine_mode));
return gpc_reg_operand (op, mode);
}
+/* Returns 1 if OP is either a constant integer valid for a DS-field or
+ a non-special register. If a register, it must be in the proper
+ mode unless MODE is VOIDmode. */
+
+int
+reg_or_aligned_short_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+{
+ if (gpc_reg_operand (op, mode))
+ return 1;
+ else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
+ return 1;
+
+ return 0;
+}
+
+
/* Return 1 if the operand is either a register or an integer whose
high-order 16 bits are zero. */
{"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
{"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
+ {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
(define_insn "*movdi_update1"
[(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
(mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
- (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
+ (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
(set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64 && TARGET_UPDATE"
(define_insn "movdi_update"
[(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
- (match_operand:DI 2 "reg_or_short_operand" "r,I")))
+ (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
(match_operand:DI 3 "gpc_reg_operand" "r,r"))
(set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
(plus:DI (match_dup 1) (match_dup 2)))]
(eq:SI (reg:CC 74)
(const_int 0)))]
"TARGET_ALTIVEC"
- "")
+ "")
(define_expand "cr6_test_for_zero_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")