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Add default entry to testcase
author
Eddie Hung
<eddie@fpgeh.com>
Thu, 11 Apr 2019 22:03:40 +0000
(15:03 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Thu, 11 Apr 2019 22:03:40 +0000
(15:03 -0700)
tests/various/muxcover.ys
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diff --git
a/tests/various/muxcover.ys
b/tests/various/muxcover.ys
index 7ac460f13e1591b4ecf9e451fdfbfbb194d73774..594e62af62bdfcadb2edf911deb29eb75a805a8d 100644
(file)
--- a/
tests/various/muxcover.ys
+++ b/
tests/various/muxcover.ys
@@
-8,12
+8,13
@@
read_verilog -formal <<EOT
3'b?1?: Y = B;
3'b1??: Y = C;
3'b000: Y = D;
+ default: Y = 'bx;
endcase
endmodule
EOT
-## Examle usage for "pmuxtree" and "muxcover"
+## Exam
p
le usage for "pmuxtree" and "muxcover"
proc
pmuxtree
@@
-35,7
+36,7
@@
read_verilog -formal <<EOT
3'b010: Y = B;
3'b100: Y = C;
3'b000: Y = D;
- default: Y = 'bx;
+
default: Y = 'bx;
endcase
endmodule
EOT