More bugfixes related to new RTLIL::IdString

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 4d71bb39408f61bf52079c0e531d5fabea0bef85..694f1d4d84d41526f68c0537a31616c61a0e5bfc 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -465,10 +465,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
                size_t pos = str.rfind('.');
                if (pos == std::string::npos)
                        log_error("Defparam `%s' does not contain a dot (module/parameter seperator) at %s:%d!\n",
-                                       RTLIL::id2cstr(str), filename.c_str(), linenum);
+                                       RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
                std::string modname = str.substr(0, pos), paraname = "\\" + str.substr(pos+1);
                if (current_scope.count(modname) == 0 || current_scope.at(modname)->type != AST_CELL)
-                       log_error("Can't find cell for defparam `%s . %s` at %s:%d!\n", RTLIL::id2cstr(modname), RTLIL::id2cstr(paraname), filename.c_str(), linenum);
+                       log_error("Can't find cell for defparam `%s . %s` at %s:%d!\n", RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paraname).c_str(), filename.c_str(), linenum);
                AstNode *cell = current_scope.at(modname), *paraset = clone();
                cell->children.insert(cell->children.begin() + 1, paraset);
                paraset->type = AST_PARASET;
@@ -1306,7 +1306,7 @@ skip_dynamic_range_lvalue_expansion:;
                        {
                                if (children.size() != 1)
                                        log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-                                                       RTLIL::id2cstr(str), int(children.size()), filename.c_str(), linenum);
+                                                       RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
 
                                AstNode *buf = children[0]->clone();
                                while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -1336,18 +1336,18 @@ skip_dynamic_range_lvalue_expansion:;
                                if (func_with_two_arguments) {
                                        if (children.size() != 2)
                                                log_error("System function %s got %d arguments, expected 2 at %s:%d.\n",
-                                                               RTLIL::id2cstr(str), int(children.size()), filename.c_str(), linenum);
+                                                               RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
                                } else {
                                        if (children.size() != 1)
                                                log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-                                                               RTLIL::id2cstr(str), int(children.size()), filename.c_str(), linenum);
+                                                               RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
                                }
 
                                if (children.size() >= 1) {
                                        while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
                                        if (!children[0]->isConst())
                                                log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n",
-                                                               RTLIL::id2cstr(str), filename.c_str(), linenum);
+                                                               RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
                                        int child_width_hint = width_hint;
                                        bool child_sign_hint = sign_hint;
                                        children[0]->detectSignWidth(child_width_hint, child_sign_hint);
@@ -1358,7 +1358,7 @@ skip_dynamic_range_lvalue_expansion:;
                                        while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
                                        if (!children[1]->isConst())
                                                log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n",
-                                                               RTLIL::id2cstr(str), filename.c_str(), linenum);
+                                                               RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
                                        int child_width_hint = width_hint;
                                        bool child_sign_hint = sign_hint;
                                        children[1]->detectSignWidth(child_width_hint, child_sign_hint);

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 72e370b94aa72c2060b3fccb753281edae7bac26..504b8d1e480678120e22c95a617f8dcb2a74f584 100644 (file)
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 
        std::string id = RTLIL::escape_id(std::string(expr, id_len));
        if (!module->wires_.count(id))
-               log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id));
+               log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
 
        expr += id_len;
        return module->wires_.at(id);
@@ -234,7 +234,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
        }
 
        if (clk_sig.size() == 0 || data_sig.size() == 0)
-               log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::id2cstr(module->name));
+               log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", log_id(module->name));
 
        for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
        {
@@ -311,7 +311,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
        }
 
        if (enable_sig.size() == 0 || data_sig.size() == 0)
-               log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::id2cstr(module->name));
+               log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name));
 
        for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
        {
@@ -480,10 +480,10 @@ struct LibertyFrontend : public Frontend {
                        if (design->has(cell_name)) {
                                if (flag_ignore_redef)
                                        continue;
-                               log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
+                               log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str());
                        }
 
-                       // log("Processing cell type %s.\n", RTLIL::id2cstr(cell_name));
+                       // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
 
                        RTLIL::Module *module = new RTLIL::Module;
                        module->name = cell_name;
@@ -501,9 +501,9 @@ struct LibertyFrontend : public Frontend {
                                        {
                                                if (!flag_ignore_miss_dir)
                                                {
-                                                       log_error("Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(), RTLIL::id2cstr(module->name));
+                                                       log_error("Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
                                                } else {
-                                                       log("Ignoring cell %s with missing or invalid direction for pin %s.\n", RTLIL::id2cstr(module->name), node->args.at(0).c_str());
+                                                       log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
                                                        delete module;
                                                        goto skip_cell;
                                                }
@@ -551,9 +551,9 @@ struct LibertyFrontend : public Frontend {
                                        {
                                                if (!flag_ignore_miss_func)
                                                {
-                                                       log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name));
+                                                       log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
                                                } else {
-                                                       log("Ignoring cell %s with missing function on output %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
+                                                       log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
                                                        delete module;
                                                        goto skip_cell;
                                                }

diff --git a/kernel/log.cc b/kernel/log.cc
index 9cabc6a836e5ae4745247308714e091ff7e54a55..01f6207ec934c5bb39789aca2a4613e3489a5542 100644 (file)
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -90,22 +90,25 @@ void logv(const char *format, va_list ap)
 
 void logv_header(const char *format, va_list ap)
 {
+       bool pop_errfile = false;
+
        log("\n");
        if (header_count.size() > 0)
                header_count.back()++;
+
+       if (int(header_count.size()) <= log_verbose_level && log_errfile != NULL) {
+               log_files.push_back(log_errfile);
+               pop_errfile = true;
+       }
+
        for (int c : header_count)
                log("%d.", c);
        log(" ");
        logv(format, ap);
        log_flush();
 
-       if (int(header_count.size()) <= log_verbose_level && log_errfile != NULL) {
-               for (int c : header_count)
-                       fprintf(log_errfile, "%d.", c);
-               fprintf(log_errfile, " ");
-               vfprintf(log_errfile, format, ap);
-               fflush(log_errfile);
-       }
+       if (pop_errfile)
+               log_files.pop_back();
 }
 
 void logv_error(const char *format, va_list ap)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7b989385e151fc3f037d50b86aba492f7f82cedd..6529603ebb1560d49b54a0ea2e56118aa01a9064 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -126,11 +126,14 @@ namespace RTLIL
 
                static inline void put_reference(int idx)
                {
+                       log_assert(global_refcount_storage_.at(idx) > 0);
+
                        if (--global_refcount_storage_.at(idx) != 0)
                                return;
 
                        global_id_index_.erase(global_id_storage_.at(idx));
                        free(global_id_storage_.at(idx));
+                       global_id_storage_.at(idx) = nullptr;
                        global_free_idx_list_.push_back(idx);
                }
 
@@ -191,7 +194,7 @@ namespace RTLIL
                }
 
                std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
-                       if (len == std::string::npos)
+                       if (len == std::string::npos || len >= strlen(c_str() + pos))
                                return std::string(c_str() + pos);
                        else
                                return std::string(c_str() + pos, len);
@@ -208,6 +211,16 @@ namespace RTLIL
                void clear() {
                        *this = IdString();
                }
+
+               // The following is a helper key_compare class. Instead of for example std::set<Cell*>
+               // use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the
+               // set has an influence on the algorithm.
+
+               template<typename T> struct compare_ptr_by_name {
+                       bool operator()(const T *a, const T *b) {
+                               return (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);
+                       }
+               };
        };
 
        static inline std::string escape_id(std::string str) {
@@ -222,18 +235,12 @@ namespace RTLIL
                return str;
        }
 
-       static inline const char *id2cstr(const std::string &str) {
-               if (str.size() > 1 && str[0] == '\\' && str[1] != '$')
-                       return str.c_str() + 1;
-               return str.c_str();
-       }
-
        static inline std::string unescape_id(RTLIL::IdString str) {
                return unescape_id(str.str());
        }
 
        static inline const char *id2cstr(const RTLIL::IdString &str) {
-               return id2cstr(str.str());
+               return log_id(str);
        }
 
        template <typename T> struct sort_by_name {
@@ -833,7 +840,11 @@ struct RTLIL::SigBit
        SigBit(const RTLIL::SigSpec &sig);
 
        bool operator <(const RTLIL::SigBit &other) const {
-               return (wire != other.wire) ? (wire < other.wire) : wire ? (offset < other.offset) : (data < other.data);
+               if (wire == other.wire)
+                       return wire ? (offset < other.offset) : (data < other.data);
+               if (wire != nullptr && other.wire != nullptr)
+                       return wire->name < other.wire->name;
+               return wire < other.wire;
        }
 
        bool operator ==(const RTLIL::SigBit &other) const {

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index b5873d188ac10fd05adddbdba2b38c4bfe0a0e35..dff31db0734c88779df4e6d2086f121e70369d97 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -122,7 +122,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
                str += stringf("(%d) ", recursion_counter);
        str += "yosys";
        if (!design->selected_active_module.empty())
-               str += stringf(" [%s]", RTLIL::id2cstr(design->selected_active_module));
+               str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
        if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) {
                if (design->selected_active_module.empty())
                        str += "*";

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 35ca2f4747463aee8b92788e61dacf763157c7c9..b4f4d26ae5728636e5e6e44f71d83831280bde1b 100644 (file)
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -490,7 +490,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode)
                                                for (auto i2 : i1.second)
                                                        limits.insert(i2);
                                        } else
-                                               log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str));
+                                               log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str());
                                } else
                                        limits.insert(RTLIL::escape_id(str));
                        }
@@ -654,7 +654,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
                if (design->selection_vars.count(set_name) > 0)
                        work_stack.push_back(design->selection_vars[set_name]);
                else
-                       log_cmd_error("Selection @%s is not defined!\n", RTLIL::id2cstr(set_name));
+                       log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
                select_filter_active_mod(design, work_stack.back());
                return;
        }
@@ -1315,7 +1315,7 @@ struct CdPass : public Pass {
                        return;
                }
 
-               log_cmd_error("No such module `%s' found!\n", RTLIL::id2cstr(modname));
+               log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname).c_str());
        }
 } CdPass;
 

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 28b4ad9907a14d5b36082159e83a851f769edb2a..50b4989dfb3524ed4adc9e60286f3259b90d37d7 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -28,7 +28,7 @@
 namespace {
        struct generate_port_decl_t {
                bool input, output;
-               std::string portname;
+               RTLIL::IdString portname;
                int index;
        };
 }

diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 1475b855eff9008e0f3d3c20aa854a283615c6eb..e51c92f9fb79aa7d5556cea824c56199884162ff 100644 (file)
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -59,9 +59,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
        if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-")
                that->cmd_error(args, argidx, "command argument error");
        
-       std::string gold_name = RTLIL::escape_id(args[argidx++]);
-       std::string gate_name = RTLIL::escape_id(args[argidx++]);
-       std::string miter_name = RTLIL::escape_id(args[argidx++]);
+       RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]);
+       RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]);
+       RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
 
        if (design->modules_.count(gold_name) == 0)
                log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 6ebac265c4ed288d9529ba0bbca7e23eff48bc8d..06af2923bd5547d2b34fb4ee0352e994752a7087 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -700,7 +700,7 @@ struct ExtractPass : public Pass {
                                log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
                                log("  primary match in %s:", id2cstr(haystack_map.at(result.graphId)->name));
                                for (auto &node : result.nodes)
-                                       log(" %s", id2cstr(node.nodeId));
+                                       log(" %s", RTLIL::unescape_id(node.nodeId).c_str());
                                log("\n");
                                for (auto &it : result.matchesPerGraph)
                                        log("  matches in %s: %d\n", id2cstr(haystack_map.at(it.first)->name), it.second);

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 2bcd3003e216e81cda97a5ce4231bb94bfc87239..374fa9bf29a6d82dca3a53967a04817f7c3ba96f 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -57,7 +57,7 @@ struct TechmapWorker
        std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
        std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
        std::map<RTLIL::Module*, bool> techmap_do_cache;
-       std::set<RTLIL::Module*> module_queue;
+       std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
 
        struct TechmapWireData {
                RTLIL::Wire *wire;
@@ -479,7 +479,7 @@ struct TechmapWorker
                                                                cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
 
                                                                log("Analyzing pattern of constant bits for this cell:\n");
-                                                               std::string new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
+                                                               RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
                                                                log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
                                                                log_assert(map->module(new_tpl_name) == nullptr);
 
@@ -824,7 +824,9 @@ struct TechmapPass : public Pass {
                                celltypeMap[it.first].insert(it.first);
                }
 
-               worker.module_queue = design->modules();
+               for (auto module : design->modules())
+                       worker.module_queue.insert(module);
+
                while (!worker.module_queue.empty())
                {
                        RTLIL::Module *module = *worker.module_queue.begin();