mess with CSR_SV_STATE set

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 1b75e1361271f5b3f90874409622e1b22ef8ffaa..84a662db1caf598f6a33c961180b787fa9c69f85 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -517,8 +517,8 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
     case CSR_SV_STATE:
     {
       // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
-      set_csr(CSR_SV_MVL, get_field(val, SV_STATE_VL )+1);
-      set_csr(CSR_SV_VL , get_field(val, SV_STATE_MVL)+1);
+      set_csr(CSR_SV_MVL, get_field(val, SV_STATE_VL ));
+      set_csr(CSR_SV_VL , get_field(val, SV_STATE_MVL));
       set_csr(CSR_SV_SUBVL , get_field(val, SV_STATE_SUBVL)+1);
       // decode (and limit) src/dest VL offsets
       reg_t srcoffs = get_field(val, SV_STATE_SRCOFFS);