[PATCH]Enable two UNSIGNED_FLOAT simplifications in simplify_unary_operation_1.

gcc/

2015-04-16  Renlin Li  <renlin.li@arm.com>

	* simplify-rtx.c (simplify_unary_operation_1): Fix a typo. Enable two
	simplifications for UNSIGNEDED_FLOAT.

gcc/testsuite/

2015-04-16  Renlin Li  <renlin.li@arm.com>

	* gcc.target/aarch64/unsigned-float.c: New.
	* gcc.target/arm/unsigned-float.c: New.

From-SVN: r222143

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5ff0a23a1bbff79756966997db98e40ec3cba809..392f679614c3706eada5731f4986ebda17961efe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-04-16  Renlin Li  <renlin.li@arm.com>
+
+       * simplify-rtx.c (simplify_unary_operation_1): Fix a typo. Enable two
+       simplifications for UNSIGNED_FLOAT.
+
 2015-04-16  Nick Clifton  <nickc@redhat.com>
 
        * config/rl78/rl78-opts.h (enum rl78_mul_types): Add MUL_G14 and

diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 5d1749829bdc883a1d61ae7a72c5e028d70918c2..4b18d3c18c2ee9f965902b43ea58288b6f31d77d 100644 (file)
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1171,7 +1171,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
          = (float_truncate:SF foo:DF).
 
          (float_truncate:DF (float_extend:XF foo:SF))
-         = (float_extend:SF foo:DF).  */
+         = (float_extend:DF foo:SF).  */
       if ((GET_CODE (op) == FLOAT_TRUNCATE
           && flag_unsafe_math_optimizations)
          || GET_CODE (op) == FLOAT_EXTEND)
@@ -1183,14 +1183,14 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
                                   XEXP (op, 0), mode);
 
       /*  (float_truncate (float x)) is (float x)  */
-      if (GET_CODE (op) == FLOAT
+      if ((GET_CODE (op) == FLOAT || GET_CODE (op) == UNSIGNED_FLOAT)
          && (flag_unsafe_math_optimizations
              || (SCALAR_FLOAT_MODE_P (GET_MODE (op))
                  && ((unsigned)significand_size (GET_MODE (op))
                      >= (GET_MODE_PRECISION (GET_MODE (XEXP (op, 0)))
                          - num_sign_bit_copies (XEXP (op, 0),
                                                 GET_MODE (XEXP (op, 0))))))))
-       return simplify_gen_unary (FLOAT, mode,
+       return simplify_gen_unary (GET_CODE (op), mode,
                                   XEXP (op, 0),
                                   GET_MODE (XEXP (op, 0)));
 
@@ -1221,7 +1221,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
          rounding can't happen.
           */
       if (GET_CODE (op) == FLOAT_EXTEND
-         || (GET_CODE (op) == FLOAT
+         || ((GET_CODE (op) == FLOAT || GET_CODE (op) == UNSIGNED_FLOAT)
              && SCALAR_FLOAT_MODE_P (GET_MODE (op))
              && ((unsigned)significand_size (GET_MODE (op))
                  >= (GET_MODE_PRECISION (GET_MODE (XEXP (op, 0)))

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2fd765cb1101a00d38b21e2285883048ca9ff0d0..f8e227965ebd544faf037142d9e2a5f820388dd8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-04-16  Renlin Li  <renlin.li@arm.com>
+
+       * gcc.target/aarch64/unsigned-unsignedfloat.c: New.
+       * gcc.target/arm/unsigned-float.c: New.
+
 2015-04-16  Richard Biener  <rguenther@suse.de>
 
        * gcc.dg/tree-ssa/ssa-ccp-36.c: New testcase.

diff --git a/gcc/testsuite/gcc.target/aarch64/unsigned-float.c b/gcc/testsuite/gcc.target/aarch64/unsigned-float.c
new file mode 100644 (file)
index 0000000..c5ad680
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/unsigned-float.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+#include <stdint.h>
+
+double
+f1 (uint16_t x)
+{
+  return (double)(float)x;
+}
+
+float
+f2 (uint16_t x)
+{
+  return (float)(double)x;
+}
+
+/* { dg-final { scan-assembler-not "fcvt" } } */

diff --git a/gcc/testsuite/gcc.target/arm/unsigned-float.c b/gcc/testsuite/gcc.target/arm/unsigned-float.c
new file mode 100644 (file)
index 0000000..bb05c85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/unsigned-float.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-march=armv7-a -O1 -mfloat-abi=softfp" } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+
+#include <stdint.h>
+
+double
+f1 (uint16_t x)
+{
+  return (double)(float)x;
+}
+
+float
+f2 (uint16_t x)
+{
+  return (float)(double)x;
+}
+
+/* { dg-final { scan-assembler-not "vcvt.(f32.f64|f64.f32)" } } */