freedreno/ir3: Drop redundant IR3_REG_HALF setup in ALU ops.
authorEric Anholt <eric@anholt.net>
Sat, 11 Apr 2020 04:54:58 +0000 (21:54 -0700)
committerMarge Bot <eric+marge@anholt.net>
Thu, 30 Apr 2020 23:36:09 +0000 (23:36 +0000)
It's set by ir3_put_dst() immediately after.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4518>

src/freedreno/ir3/ir3_compiler_nir.c

index 1ada43f4ea6d6aa4177a19216c713215c13adc4c..2027fb88c7d68e52aa8d058f125eac464d0abb43 100644 (file)
@@ -733,12 +733,6 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
                dst[0] = ir3_n2b(b, dst[0]);
        }
 
-       if (nir_dest_bit_size(alu->dest.dest) < 32) {
-               for (unsigned i = 0; i < dst_sz; i++) {
-                       dst[i]->regs[0]->flags |= IR3_REG_HALF;
-               }
-       }
-
        ir3_put_dst(ctx, &alu->dest.dest);
 }