Improve tests/ice40/macc.ys for SB_MAC16

diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
index 63a3d3a74b2d46f30da320d1bf0d66bcdbb64adb..6c3676c8314064a5c351a43e26f2beb4f569ab9d 100644 (file)
--- a/tests/ice40/macc.v
+++ b/tests/ice40/macc.v
@@ -2,8 +2,8 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
 */
 module top(clk,a,b,c,set);
-parameter A_WIDTH = 4;
-parameter B_WIDTH = 3;
+parameter A_WIDTH = 6 /*4*/;
+parameter B_WIDTH = 6 /*3*/;
 input set;
 input clk;
 input signed [(A_WIDTH - 1):0] a;

diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
index fe5b5f662f9d5e0ac49aa23918d0afbee67f3c0e..0f4c19be57f8f4e738b4462a82c7e7cd9869776c 100644 (file)
--- a/tests/ice40/macc.ys
+++ b/tests/ice40/macc.ys
@@ -1,10 +1,13 @@
 read_verilog macc.v
 proc
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
+async2sync
+equiv_opt -run prove: -assert null
+
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 38 t:SB_LUT4
-select -assert-count 3 t:SB_CARRY
-select -assert-count 7 t:SB_DFFSR
-select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D
+select -assert-count 1 t:SB_MAC16
+select -assert-none t:SB_MAC16 %% t:* %D