# Reduce mode
Reduction in SVP64 is deterministic and somewhat of a misnomer. A normal
-Vector ISA would have explicit Reduce opcodes with defibed characteristics
+Vector ISA would have explicit Reduce opcodes with defined characteristics
per operation: in SX Aurora there is even an additional scalar argument
containing the initial reduction value. SVP64 fundamentally has to
utilise *existing* Scalar Power ISA v3.0B operations, which presents some