(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 985c192cb8295ee63daa2e5072969303d046a71a..c04868f9351a48de0c5988a5442d2be8db92eaa3 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -7,6 +7,7 @@ Links:
 * [[sv/branches]]
 * [[openpower/isa/sprset]]
 * [[openpower/isa/condition]]
+* [[openpower/isa/comparefixed]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element