Remove hack now that ports work properly

--HG--
extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 170c78d3a225044203b5e390283a2a71d52b2503..12a47fb3e71908a32138ff58a6dbb063329fe8f5 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -452,12 +452,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    if (cpu->_status == DcacheWaitResponse)
-        cpu->completeDataAccess(pkt);
-    else if (cpu->_status == IcacheWaitResponse)
-        cpu->completeIfetch(pkt);
-    else
-        assert("OOPS" && 0);
+    cpu->completeIfetch(pkt);
     return true;
 }