Do not eagerly fix port widths on parameterized cells

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 4786aacaf6ba743338385de1655903d1b826b0d5..037fdb3b2fd7dd530de47961566841c26780297d 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -625,6 +625,9 @@ struct HierarchyPass : public Pass {
                        for (auto module : design->modules())
                        for (auto cell : module->cells())
                        {
+                               if (GetSize(cell->parameters) != 0)
+                                       continue;
+
                                Module *m = design->module(cell->type);
 
                                if (m == nullptr)