(no commit message)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 85759aecddc20b3e84758f1c71c1b40f5981d149..f44212fff9ecee61214228c4129d9b4491ef126b 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -115,7 +115,7 @@ microarchitecture, especially at the decode phase.
 Instead, Intel, in 2012, specifically added a `mulx` instruction, allowing
 both HI and LO halves of the multiply to reach registers.  If done as a
 multiply-and-accumulate this becomes quite an expensive operation:
-3 64-Bit in, 2 64-bit registers out).
+(3 64-Bit in, 2 64-bit registers out).
 
 Long-multiplication may be performed a row at a time, starting
 with B0: