(no commit message)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 408a27bc88910fbec94de374067cbb91218a9844..cdcddc61edf8f4f213e4f257c8b2045b8cba34a6 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -135,7 +135,8 @@ of Knuth M: <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/b
 
 ```
       // this becomes the basis for sv.madded in RS=RC Mode,
-      // where k is RC
+      // where k is RC. k takes the upper half of product
+      // and adds it in on the next iteration
       k = 0;
       for (i = 0; i < m; i++) {
          unsigned product = u[i]*v[j] + k;
@@ -168,7 +169,7 @@ RA*RB+RC+RD cannot overflow, so does not require
 setting an additional CA flag. We first cover the chain of
 RA*RB+RC as follows:
 
-    RT0, RC0 = RA0 * RB0 + RC
+    RT0, RC0 = RA0 * RB0 + 0
           |
           +----------------+
                            |