r300->hw.unk4E88.cmd[0] = cmducs(0x4E88, 1);
ALLOC_STATE( unk4EA0, always, 3, "unk4EA0 R350 only", 0 );
r300->hw.unk4EA0.cmd[0] = cmducs(0x4EA0, 2);
- ALLOC_STATE( zc, always, R300_ZC_CMDSIZE, "zc", 0 );
- r300->hw.zc.cmd[R300_ZC_CMD_0] = cmducs(R300_RB3D_ZCNTL_0, 2);
- ALLOC_STATE( unk4F08, always, 2, "unk4F08", 0 );
- r300->hw.unk4F08.cmd[0] = cmducs(0x4F08, 1);
+ ALLOC_STATE( zs, always, R300_ZS_CMDSIZE, "zstencil", 0 );
+ r300->hw.zs.cmd[R300_ZS_CMD_0] = cmducs(R300_RB3D_ZSTENCIL_CNTL_0, 3);
ALLOC_STATE( unk4F10, always, 5, "unk4F10", 0 );
r300->hw.unk4F10.cmd[0] = cmducs(0x4F10, 4);
ALLOC_STATE( zb, always, R300_ZB_CMDSIZE, "zb", 0 );
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E50);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E88);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4EA0);
- insert_at_tail(&r300->hw.atomlist, &r300->hw.zc);
- insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F08);
+ insert_at_tail(&r300->hw.atomlist, &r300->hw.zs);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F10);
insert_at_tail(&r300->hw.atomlist, &r300->hw.zb);
insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F28);
#define R300_CB_PITCH 3
#define R300_CB_CMDSIZE 4
-#define R300_ZC_CMD_0 0
-#define R300_ZC_CNTL_0 1
-#define R300_ZC_CNTL_1 2
-#define R300_ZC_CMDSIZE 3
+#define R300_ZS_CMD_0 0
+#define R300_ZS_CNTL_0 1
+#define R300_ZS_CNTL_1 2
+#define R300_ZS_CNTL_2 3
+#define R300_ZS_CMDSIZE 4
#define R300_ZB_CMD_0 0
#define R300_ZB_OFFSET 1
struct r300_state_atom vpt; /* viewport (1D98) */
struct r300_state_atom unk2080; /* (2080) */
+ struct r300_state_atom vof; /* VAP output format register 0x2090 */
struct r300_state_atom vte; /* (20B0) */
struct r300_state_atom unk2134; /* (2134) */
struct r300_state_atom unk2140; /* (2140) */
struct r300_state_atom unk2220; /* (2220) */
struct r300_state_atom unk2288; /* (2288) */
struct r300_state_atom pvs; /* pvs_cntl (22D0) */
- struct r300_state_atom vof; /* VAP output format register 0x2090 */
struct r300_state_atom gb_enable; /* (4008) */
struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
struct r300_state_atom unk4200; /* (4200) */
struct r300_state_atom unk4E50; /* (4E50) */
struct r300_state_atom unk4E88; /* (4E88) */
struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware.. */
- struct r300_state_atom zc; /* z control (4F00) */
- struct r300_state_atom unk4F08; /* (4F08) */
+ struct r300_state_atom zs; /* zstencil control (4F00) */
struct r300_state_atom unk4F10; /* (4F10) */
struct r300_state_atom zb; /* z buffer (4F20) */
struct r300_state_atom unk4F28; /* (4F28) */
r300->hw.vpi.cmd[7] = VP_ZERO();
r300->hw.vpi.cmd[8] = 0;
- R300_STATECHANGE(r300, zc);
+ R300_STATECHANGE(r300, zs);
if (flags & CLEARBUFFER_DEPTH) {
- r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0x6; // test and write
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_ALWAYS;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] = 0x6; // test and write
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] = (R300_ZS_ALWAYS<<R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
/*
R300_STATECHANGE(r300, zb);
r300->hw.zb.cmd[R300_ZB_OFFSET] =
r300->radeon.radeonScreen->depthPitch;
*/
} else {
- r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0; // disable
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] = 0; // disable
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] = 0;
}
/* Make sure we have enough space */
/* gap */
/* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */
/* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */
-#define R300_RB3D_ZCNTL_0 0x4F00
+#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */
# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
# define R300_RB3D_Z_WRITE_ONLY 0x00000006
-#define R300_RB3D_ZCNTL_1 0x4F04
-# define R300_Z_TEST_NEVER (0 << 0) /* GUESS (based on R200) */
-# define R300_Z_TEST_LESS (1 << 0)
-# define R300_Z_TEST_LEQUAL (2 << 0)
-# define R300_Z_TEST_EQUAL (3 << 0) /* GUESS */
-# define R300_Z_TEST_GEQUAL (4 << 0) /* GUESS */
-# define R300_Z_TEST_GREATER (5 << 0) /* GUESS */
-# define R300_Z_TEST_NEQUAL (6 << 0)
-# define R300_Z_TEST_ALWAYS (7 << 0)
-# define R300_Z_TEST_MASK (7 << 0)
+
+#define R300_RB3D_ZSTENCILCNTL_1 0x4F04
+ /* functions */
+# define R300_ZS_NEVER 0
+# define R300_ZS_LESS 1
+# define R300_ZS_LEQUAL 2
+# define R300_ZS_EQUAL 3
+# define R300_ZS_GEQUAL 4
+# define R300_ZS_GREATER 5
+# define R300_ZS_NOTEQUAL 6
+# define R300_ZS_ALWAYS 7
+# define R300_ZS_MASK 7
+ /* operations */
+# define R300_ZS_KEEP 0
+# define R300_ZS_ZERO 1
+# define R300_ZS_REPLACE 2
+# define R300_ZS_INCR 3
+# define R300_ZS_DECR 4
+# define R300_ZS_INVERT 5
+# define R300_ZS_INCR_WRAP 6
+# define R300_ZS_DECR_WRAP 7
+
+
+# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
+# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
+# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
+# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9
+# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12
+# define R300_RB3D_ZS1_STENCIL_FUNC_SHIFT 15
+# define R300_RB3D_ZS1_STENCIL_FAIL_OP_SHIFT 18
+# define R300_RB3D_ZS1_STENCIL_ZPASS_OP_SHIFT 21
+# define R300_RB3D_ZS1_STENCIL_ZFAIL_OP_SHIFT 24
+
+
+
+#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
+# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
+# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8
+# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16
+
/* gap */
#define R300_RB3D_DEPTHOFFSET 0x4F20
#define R300_RB3D_DEPTHPITCH 0x4F24
R300_STATECHANGE(rmesa, vte);
#endif
+
/* Magic register - note it is right after 20b0 */
e32(0x0000000c);
}
-
+
r300EmitState(rmesa);
#if 0
reg_start(R300_RB3D_COLORMASK, 0);
e32(0xf);
+
+ vsf_start_fragment(0x406, 4);
+ efloat(0.0);
+ efloat(0.0);
+ efloat(0.0);
+ efloat(1.0);
+
+ vsf_start_fragment(0x400, 4);
+ efloat(0.0);
+ efloat(0.0);
+ efloat(0.0);
+ efloat(1.0);
#endif
- /* ----------------------------------- */
/* We need LOAD_VBPNTR to setup AOS_ATTR fields.. the offsets are irrelevant */
r300EmitLOAD_VBPNTR(rmesa, 0);
#include "swrast_setup/swrast_setup.h"
#include "array_cache/acache.h"
#include "tnl/tnl.h"
+#include "texformat.h"
#include "radeon_ioctl.h"
#include "radeon_state.h"
break;
case GL_DEPTH_TEST:
- R300_STATECHANGE(r300, zc);
+ R300_STATECHANGE(r300, zs);
if (state) {
if (ctx->Depth.Mask)
} else
newval = 0;
- r300->hw.zc.cmd[R300_ZC_CNTL_0] = newval;
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] = newval;
break;
case GL_CULL_FACE:
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
- R300_STATECHANGE(r300, zc);
+ R300_STATECHANGE(r300, zs);
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
+
switch(func) {
case GL_NEVER:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_NEVER;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_NEVER << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_LESS:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_LESS;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_LESS << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_EQUAL:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_EQUAL;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_EQUAL << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_LEQUAL:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_LEQUAL;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_LEQUAL << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_GREATER:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_GREATER;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_GREATER << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_NOTEQUAL:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_NEQUAL;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_NOTEQUAL << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_GEQUAL:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_GEQUAL;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_GEQUAL << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
case GL_ALWAYS:
- r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_Z_TEST_ALWAYS;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] |= R300_ZS_ALWAYS << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
break;
}
+
+ fprintf(stderr, "ZS_CNTL_1=%08x\n", r300->hw.zs.cmd[R300_ZS_CNTL_1]);
}
if (!ctx->Depth.Test)
return;
- R300_STATECHANGE(r300, zc);
- r300->hw.zc.cmd[R300_ZC_CNTL_0] = mask
+ R300_STATECHANGE(r300, zs);
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] = mask
? R300_RB3D_Z_TEST_AND_WRITE : R300_RB3D_Z_TEST;
}
)
-static GLuint translate_texture_format(GLcontext *ctx, GLint tex_unit, GLuint format, GLint IntFormat)
+static GLuint translate_texture_format(GLcontext *ctx, GLint tex_unit, GLuint format, GLint IntFormat,
+ struct gl_texture_format *tex_format)
{
const struct gl_texture_unit *texUnit= &ctx->Texture.Unit[tex_unit];
int i=0; /* number of alpha args .. */
texUnit->_ReallyEnabled,
_mesa_lookup_enum_by_nr(texUnit->EnvMode));
#endif
-
+
+ if(tex_format==NULL){
+ fprintf(stderr, "Aeiii ! tex_format==NULL !!\n");
+ return 0;
+ }
+
+ switch(tex_format->MesaFormat){
+ case MESA_FORMAT_RGBA8888:
+ return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8);
+ default:
+ fprintf(stderr, "Do not know format %s\n", _mesa_lookup_enum_by_nr(tex_format->MesaFormat));
+ return 0;
+ }
+
switch(IntFormat){
case 4:
case GL_RGBA:
case GL_RGBA8:
- fmt=R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8);
break;
case 3:
case GL_RGB8:
- fmt=R300_EASY_TX_FORMAT(Z, Y, X, ONE, W8Z8Y8X8);
+ fmt=R300_EASY_TX_FORMAT(Y, Z, W, ONE, W8Z8Y8X8);
break;
default:
return 0;
}
- #if 0
+ #if 1
//fmt &= 0x00fff;
//fmt |= ((format) & 0xff00)<<4;
fprintf(stderr, "NumArgsRGB=%d NumArgsA=%d\n",
fprintf(stderr, "fmt=%08x\n", fmt);
#endif
- //return fmt;
+ return fmt;
/* Size field in format specific first */
switch(FORMAT_HASH(
texUnit->_CurrentCombine->OperandRGB[i] -GL_SRC_COLOR,
for(i=0;i<mtu;i++){
if(ctx->Texture.Unit[i].Enabled){
t=r300->state.texture.unit[i].texobj;
+ fprintf(stderr, "format=%08x\n", r300->state.texture.unit[i].format);
r300->state.texture.tc_count++;
if(t==NULL){
fprintf(stderr, "Texture unit %d enabled, but corresponding texobj is NULL, using default object.\n", i);
/*r300->hw.tex.unknown1.cmd[R300_TEX_VALUE_0+i]=(rand()%0xffffffff) & (~0x1fff);*/
r300->hw.tex.size.cmd[R300_TEX_VALUE_0+i]=t->size;
r300->hw.tex.format.cmd[R300_TEX_VALUE_0+i]=t->format;
+ //fprintf(stderr, "t->format=%08x\n", t->format);
r300->hw.tex.offset.cmd[R300_TEX_VALUE_0+i]=r300->radeon.radeonScreen->fbLocation+t->offset;
r300->hw.tex.unknown4.cmd[R300_TEX_VALUE_0+i]=0x0;
r300->hw.tex.unknown5.cmd[R300_TEX_VALUE_0+i]=0x0;
/* We don't know how to set this yet */
//value from r300_lib.c for RGB24
//r300->hw.tex.format.cmd[R300_TEX_VALUE_0+i]=0x88a0c;
+ #if 0
r300->hw.tex.format.cmd[R300_TEX_VALUE_0+i]=translate_texture_format(ctx, i, t->format,
- r300->state.texture.unit[i].texobj!=NULL?t->base.tObj->Image[0][0]->IntFormat:3);
-
+ r300->state.texture.unit[i].texobj!=NULL?t->base.tObj->Image[0][0]->IntFormat:3,
+ r300->state.texture.unit[i].texobj!=NULL?t->base.tObj->Image[0][0]->TexFormat:NULL);
+ #endif
#if 0
fprintf(stderr, "Format=%s IntFormat=%08x MesaFormat=%08x BaseFormat=%s IsCompressed=%d Target=%s\n",
/* Use the code below to quickly find matching texture
formats. Requires an app that displays the same texture
repeatedly */
- #if 1
+ #if 0
if(r300->hw.tex.format.cmd[R300_TEX_VALUE_0+i]==0){
static int fmt=0x0;
static int k=0;
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s\n", __FUNCTION__);
+ /* This is a place to initialize registers which
+ have bitfields accessed by different functions
+ and not all bits are used */
+ #if 0
+ r300->hw.zs.cmd[R300_ZS_CNTL_0] = 0;
+ r300->hw.zs.cmd[R300_ZS_CNTL_1] = 0;
+ r300->hw.zs.cmd[R300_ZS_CNTL_2] = 0xffff00;
+ #endif
+
+ /* go and compute register values from GL state */
+
r300UpdateWindow(ctx);
r300ColorMask(ctx,
r300_set_blend_state(ctx);
r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
-//BEGIN: TODO
+ /* Initialize magic registers
+ TODO : learn what they really do, or get rid of
+ those we don't have to touch */
r300->hw.unk2080.cmd[1] = 0x0030045A;
r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
r300->hw.unk4EA0.cmd[1] = 0x00000000;
r300->hw.unk4EA0.cmd[2] = 0xffffffff;
- r300->hw.unk4F08.cmd[1] = 0x00FFFF00;
-
r300->hw.unk4F10.cmd[1] = 0x00000002; // depthbuffer format?
r300->hw.unk4F10.cmd[2] = 0x00000000;
r300->hw.unk4F10.cmd[3] = 0x00000003;
(rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16);
(void)format;
+ #if 0
+ fprintf(stderr, "InternalFormat=%s type=%s format=%s\n",
+ _mesa_lookup_enum_by_nr(internalFormat),
+ _mesa_lookup_enum_by_nr(type),
+ _mesa_lookup_enum_by_nr(format));
+ #endif
+
switch (internalFormat) {
case 4:
case GL_RGBA:
static const struct {
GLuint format, filter;
-} tx_table[] = {
+} tx_table0[] = {
_ALPHA(RGBA8888),
_ALPHA_REV(RGBA8888),
_ALPHA(ARGB8888),
_COLOR(L8),
_ALPHA(I8), _INVALID(CI8), _YUV(YCBCR), _YUV(YCBCR_REV),};
+static const struct {
+ GLuint format, filter;
+} tx_table[] = {
+ {R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8), 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+ {7, 0},
+ {8, 0},
+ {9, 0},
+ {10, 0},
+ {11, 0},
+ {12, 0},
+ {13, 0},
+ {14, 0},
+ {15, 0},
+ {16, 0},
+ {17, 0},
+ };
+
+
#undef _COLOR
#undef _ALPHA
#undef _INVALID
+
+
/**
* This function computes the number of bytes of storage needed for
* the given texture object (all mipmap levels, all cube faces).
t->filter &= ~R200_YUV_TO_RGB;
#endif
if (VALID_FORMAT(baseImage->TexFormat->MesaFormat)) {
- t->format |=
+ t->format =
tx_table[baseImage->TexFormat->MesaFormat].format;
-#if 0
+#if 1
t->filter |=
tx_table[baseImage->TexFormat->MesaFormat].filter;
#endif
t->filter &= ~R200_MAX_MIP_LEVEL_MASK;
t->filter |= (numLevels - 1) << R200_MAX_MIP_LEVEL_SHIFT;
#endif
+ #if 0
t->format &= ~(R200_TXFORMAT_WIDTH_MASK |
R200_TXFORMAT_HEIGHT_MASK |
R200_TXFORMAT_CUBIC_MAP_ENABLE |
R200_TXFORMAT_F5_HEIGHT_MASK);
t->format |= ((log2Width << R200_TXFORMAT_WIDTH_SHIFT) |
(log2Height << R200_TXFORMAT_HEIGHT_SHIFT));
-
+ #endif
+
t->format_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK);
if (tObj->Target == GL_TEXTURE_3D) {
t->format_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT);
~(R200_TXC_SCALE_MASK);
GLuint alpha_scale = rmesa->hw.pix[unit].cmd[PIX_PP_TXABLEND2] &
~(R200_TXA_DOT_ALPHA | R200_TXA_SCALE_MASK);
-
+ #endif
+
+ GLuint color_scale=0, alpha_scale=0;
+
/* texUnit->_Current can be NULL if and only if the texture unit is
* not actually enabled.
*/
*/
/* Don't cache these results.
*/
+ #if 0
rmesa->state.texture.unit[unit].format = 0;
+ #endif
rmesa->state.texture.unit[unit].envMode = 0;
+
if (!texUnit->_ReallyEnabled) {
if (unit == 0) {
color_combine =
*/
}
+ fprintf(stderr, "color_combine=%08x alpha_combine=%08x color_scale=%08x alpha_scale=%08x\n");
+
+ #if 0
if (rmesa->hw.pix[unit].cmd[PIX_PP_TXCBLEND] != color_combine ||
rmesa->hw.pix[unit].cmd[PIX_PP_TXABLEND] != alpha_combine ||
rmesa->hw.pix[unit].cmd[PIX_PP_TXCBLEND2] != color_scale ||
rmesa->recheck_texgen[unit] = 0;
rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
}
+ #endif
format = tObj->Image[0][tObj->BaseLevel]->Format;
if (rmesa->state.texture.unit[unit].format != format ||
rmesa->state.texture.unit[unit].envMode != texUnit->EnvMode) {
- rmesa->state.texture.unit[unit].format = format;
+ //rmesa->state.texture.unit[unit].format = format;
rmesa->state.texture.unit[unit].envMode = texUnit->EnvMode;
if (!r300UpdateTextureEnv(ctx, unit)) {
return GL_FALSE;
}
}
- #endif
FALLBACK(&rmesa->radeon, RADEON_FALLBACK_BORDER_MODE, t->border_fallback);
return !t->border_fallback;