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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
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   [[ls001/discussion]]
 
 This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
-Vectorisation Concept that may be applied to **all and any** suitable
+Vectorisation Concept that may be orthogonally applied to **all and any** suitable
 Scalar instructions, present and future, in the Scalar Power ISA.
 The Vectorisation System is called
 ["Simple-V"](https://libre-soc.org/openpower/sv/)
 and the Prefix Format is called
 ["SVP64"](https://libre-soc.org/openpower/sv/).
 **Simple-V is not a Traditional Vector ISA and therefore
-does not add Vector opcodes**.
+does not add Vector opcodes or regfiles**.
 An ISA Concept similar to Simple-V was originally invented in 1994 by
 Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not
 have an Out-of-Order Microarchitecture on which to best exploit it.