Add missing break statemenets.

diff --git a/sim/moxie/ChangeLog b/sim/moxie/ChangeLog
index fdad6c5b22391f55cd7c89d78a1b178e42547cdf..c528de318461d496402b45e05d8f919ea5e81963 100644 (file)
--- a/sim/moxie/ChangeLog
+++ b/sim/moxie/ChangeLog
@@ -1,3 +1,7 @@
+2009-05-09  Anthony Green  <green@moxielogic.com>
+
+       * interp.c (sim_resume): Add missing breaks in switch.
+
 2008-10-03  Anthony Green  <green@moxielogic.com>
 
        * interp.c (sim_resume): Add support for ldo.b, sto.b, ldo.s, sto.s.

diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 2be561ce33cc56456d113f0dd44648f9fc219464..dd87648b5ff7730fb3eb2bd052b8582d0ef9f2d7 100644 (file)
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -460,6 +460,7 @@ sim_resume (sd, step, siggnal)
                    TRACE("gsr");
                    cpu.asregs.regs[a] = cpu.asregs.sregs[v];
                  }
+                 break;
                case 0x03: /* ssr */
                  {
                    int a = (inst >> 8) & 0xf;
@@ -467,6 +468,7 @@ sim_resume (sd, step, siggnal)
                    TRACE("ssr");
                    cpu.asregs.sregs[v] = cpu.asregs.regs[a];
                  }
+                 break;
                default:
                  TRACE("SIGILL2");
                  cpu.asregs.exception = SIGILL;