mem: Allowed tagged instruction prefetching in stride prefetcher

For systems with a tightly coupled L2, a stride-based prefetcher may observe
access requests from both instruction and data L1 caches.  However, the PC
address of an instruction miss gives no relevant training information to the
stride based prefetcher(there is no stride to train).  In theses cases, its
better if the L2 stride prefetcher simply reverted back to a simple N-block
ahead prefetcher.  This patch enables this option.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 7d7aeed3219b85f07ad28d68fc14823381518506..c4b6b8845c8cf6f3e0f4fdd2ad61057541c42e31 100644 (file)
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -65,6 +65,8 @@ class BasePrefetcher(ClockedObject):
          "Only prefetch on read requests (write requests ignored)")
     on_prefetch = Param.Bool(True,
          "Let lower cache prefetcher train on prefetch requests")
+    inst_tagged = Param.Bool(True,
+         "Perform a tagged prefetch for instruction fetches always")
     sys = Param.System(Parent.any, "System this device belongs to")
 
 class GHBPrefetcher(BasePrefetcher):

diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index a7abf48094b82f593cba29c14247773d1a019665..c4cf2023aa560236318cd434d8fd49a37c45bce1 100644 (file)
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -66,6 +66,23 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
     assert(master_id < Max_Contexts);
     std::list<StrideEntry*> &tab = table[master_id];
 
+    // Revert to simple N-block ahead prefetch for instruction fetches
+    if (instTagged && pkt->req->isInstFetch()) {
+        for (int d = 1; d <= degree; d++) {
+            Addr new_addr = data_addr + d * blkSize;
+            if (pageStop && !samePage(data_addr, new_addr)) {
+                // Spanned the page, so now stop
+                pfSpanPage += degree - d + 1;
+                return;
+            }
+            DPRINTF(HWPrefetch, "queuing prefetch to %x @ %d\n",
+                    new_addr, latency);
+            addresses.push_back(new_addr);
+            delays.push_back(latency);
+        }
+        return;
+    }
+
     /* Scan Table for instAddr Match */
     std::list<StrideEntry*>::iterator iter;
     for (iter = tab.begin(); iter != tab.end(); iter++) {

diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index b02d97d56947194b6008c55d63f2e326c1cfd7e2..0e31984f96fc421d802abec73a3235cd16b2b5ae 100644 (file)
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -76,10 +76,12 @@ class StridePrefetcher : public BasePrefetcher
 
     std::list<StrideEntry*> table[Max_Contexts];
 
+    bool instTagged;
+
   public:
 
     StridePrefetcher(const Params *p)
-        : BasePrefetcher(p)
+        : BasePrefetcher(p), instTagged(p->inst_tagged)
     {
     }