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diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn
index 238cd125fcfd4bb35770a96d3c8c3bc48ca69dbf..ef2d03828cc50b8d6371f3019b83ad9ac9202c40 100644 (file)
--- a/openpower/sv/rfc/ls011.mdwn
+++ b/openpower/sv/rfc/ls011.mdwn
@@ -1,5 +1,80 @@
-TODO
+# LD/ST-Update-PostIncrement
+
+TODO (key stub notes below)
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=1048>
 
+The following instructions are proposed to be added in EXT2xx,
+duplicating LD/ST-Update functionality but moving the update
+of RA to *after* the Memory operation.  These types of
+instructions are already present in x86 (sort-of).
+
+* x86 chose that store should be pre-indexed and load should be post-indexed
+* Power ISA chose everything to be pre-indexed
+
+<https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
+
+
+```
+# LD/ST-Postincrement
+lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+# FP LD/ST-Postincrement
+lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
+lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
+stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
+stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+```
+
+# Example
+
+** Load Byte and Zero with Post-Update**
+
+D-Form
+
+* lbzup RT,D(RA)
+
+Pseudo-code:
+
+```
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + EXTS(D)
+```
+
+Special Registers Altered:
+
+```
+    None
+```
+
+where the same pseudocode for `lbzu` is:
+
+```
+    EA <- (RA) + EXTS(D)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- EA
+```
+
 [[!tag opf_rfc]]