uint32_t tf_param;
};
+static const VkPipelineMultisampleStateCreateInfo *
+radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
+ return pCreateInfo->pMultisampleState;
+ return NULL;
+}
+
bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *variant = NULL;
const struct radv_graphics_pipeline_create_info *extra)
{
const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
- const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
+ const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
struct radv_blend_state blend = {0};
unsigned mode = V_028808_CB_NORMAL;
int i;
struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
- const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
+ const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
struct radv_multisample_state *ms = &pipeline->graphics.ms;
unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
bool out_of_order_rast = false;
if (pCreateInfo->pTessellationState)
key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
-
- if (pCreateInfo->pMultisampleState &&
- pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
- uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
- uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
+ const VkPipelineMultisampleStateCreateInfo *vkms =
+ radv_pipeline_get_multisample_state(pCreateInfo);
+ if (vkms && vkms->rasterizationSamples > 1) {
+ uint32_t num_samples = vkms->rasterizationSamples;
+ uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
key.num_samples = num_samples;
key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
}