i915g: fix transfer coherency

The kernel drm takes care of all coherency as long as we don't forget
to submit all outstanding commands in the batchbuffer ...

Also move batchbuffer initialization up because otherwise transfers
for some helper textures fail with a segmentation fault.

And kill the dead code, flushes should now be correct everywhere.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/src/gallium/drivers/i915/i915_context.c b/src/gallium/drivers/i915/i915_context.c
index 5dbf0cfcbf12b07a53f4c3aca367308ec8fec83b..cb3de82a104417264f53273eb45c0d327b711cd0 100644 (file)
--- a/src/gallium/drivers/i915/i915_context.c
+++ b/src/gallium/drivers/i915/i915_context.c
@@ -151,6 +151,10 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    util_slab_create(&i915->transfer_pool, sizeof(struct pipe_transfer),
                     16, UTIL_SLAB_SINGLETHREADED);
 
+   /* Batch stream debugging is a bit hacked up at the moment:
+    */
+   i915->batch = i915->iws->batchbuffer_create(i915->iws);
+
    /*
     * Create drawing context and plug our rendering stage into it.
     */
@@ -183,9 +187,5 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    i915->dynamic_dirty = ~0;
    i915->flush_dirty = 0;
 
-   /* Batch stream debugging is a bit hacked up at the moment:
-    */
-   i915->batch = i915->iws->batchbuffer_create(i915->iws);
-
    return &i915->base;
 }

diff --git a/src/gallium/drivers/i915/i915_flush.c b/src/gallium/drivers/i915/i915_flush.c
index 87966d98079a3f1becb7932fdd1b126e4aadbb64..a5407cfd18419b1d08a630fb7d9d094cd9ab6061 100644 (file)
--- a/src/gallium/drivers/i915/i915_flush.c
+++ b/src/gallium/drivers/i915/i915_flush.c
@@ -45,28 +45,6 @@ static void i915_flush_pipe( struct pipe_context *pipe,
 
    draw_flush(i915->draw);
 
-#if 0
-   /* Do we need to emit an MI_FLUSH command to flush the hardware
-    * caches?
-    */
-   /* XXX These flags are now implicit. All of them. */
-   if (flags & (PIPE_FLUSH_RENDER_CACHE | PIPE_FLUSH_TEXTURE_CACHE)) {
-      unsigned flush = MI_FLUSH;
-      
-      if (!(flags & PIPE_FLUSH_RENDER_CACHE))
-        flush |= INHIBIT_FLUSH_RENDER_CACHE;
-
-      if (flags & PIPE_FLUSH_TEXTURE_CACHE)
-        flush |= FLUSH_MAP_CACHE;
-
-      if (!BEGIN_BATCH(1)) {
-        FLUSH_BATCH(NULL);
-        assert(BEGIN_BATCH(1));
-      }
-      OUT_BATCH( flush );
-   }
-#endif
-
    if (i915->batch->map == i915->batch->ptr) {
       return;
    }

diff --git a/src/gallium/drivers/i915/i915_resource_texture.c b/src/gallium/drivers/i915/i915_resource_texture.c
index cfb72e9dcacf658eabdc19a7a69b63172116d490..7816925d2306bdda8bae86804a0cd21f8033fb05 100644 (file)
--- a/src/gallium/drivers/i915/i915_resource_texture.c
+++ b/src/gallium/drivers/i915/i915_resource_texture.c
@@ -759,6 +759,9 @@ i915_texture_transfer_map(struct pipe_context *pipe,
       assert(box->z == 0);
    offset = i915_texture_offset(tex, transfer->level, box->z);
 
+   /* TODO this is a sledgehammer */
+   pipe->flush(pipe, NULL);
+
    map = iws->buffer_map(iws, tex->buffer,
                          (transfer->usage & PIPE_TRANSFER_WRITE) ? TRUE : FALSE);
    if (map == NULL)