<bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
<bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
</reg32>
- <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
- <reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
- <reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
+ <bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
+ <bitfield name="CLIP_MASK" low="0" high="7"/>
+ <bitfield name="CULL_MASK" low="8" high="15"/>
+ </bitset>
+ <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
+ <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
+ <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
<enum name="a6xx_layer_type">
<value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
<!-- always 0x0 -->
<reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
- <!-- always 0x0 ? -->
- <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
-
- <reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
- <bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
- </reg32>
-
- <reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
+ <bitset name="a6xx_gras_layer_cntl" inline="yes">
+ <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
+ </bitset>
+ <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
+ <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
+ <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
<reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
<reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
- <!-- always 0x00ffff00 ? */ -->
- <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
- <reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
- <reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
-
- <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
+ <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
+ <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
+ <!-- there can be up to 8 total clip/cull distance outputs,
+ but apparenly VPC can only deal with vec4, so when there are
+ more than 4 outputs a second location needs to be programmed
+ -->
+ <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
+ <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
+ </bitset>
+ <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
+ <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
+ <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
- <reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
+ <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
- </reg32>
+ <bitfield name="UNKLOC" low="8" high="15" type="uint"/>
+ </bitset>
+
+ <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
+ <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
+ <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
- <reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
<reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
<reg32 offset="0x9108" name="VPC_POLYGON_MODE">
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
<!-- always 0x0 ? -->
<reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
- <reg32 offset="0x9301" name="VPC_PACK">
+ <bitset name="a6xx_vpc_xs_pack" inline="yes">
<doc>
num of varyings plus four for gl_Position (plus one if gl_PointSize)
plus # of transform-feedback (streamout) varyings if using the
</doc>
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
- <!--
- This seems to be the OUTLOC for the psize output. It could possibly
- be the max-OUTLOC position, but it is only set when VS writes psize
- (and blob always puts psize at highest OUTLOC)
- -->
<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
- </reg32>
-
- <reg32 offset="0x9302" name="VPC_PACK_GS">
- <doc>
- num of varyings plus four for gl_Position (plus one if gl_PointSize)
- plus # of transform-feedback (streamout) varyings if using the
- hw streamout (rather than stg instructions in shader)
- </doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
- <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
- <!--
- This seems to be the OUTLOC for the psize output. It could possibly
- be the max-OUTLOC position, but it is only set when VS writes psize
- (and blob always puts psize at highest OUTLOC)
- -->
- <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
- </reg32>
-
- <reg32 offset="0x9303" name="VPC_PACK_3">
- <doc>
- domain shader version of VPC_PACK
- </doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
- <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
- <!--
- This seems to be the OUTLOC for the psize output. It could possibly
- be the max-OUTLOC position, but it is only set when VS writes psize
- (and blob always puts psize at highest OUTLOC)
- -->
- <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
- </reg32>
+ </bitset>
+ <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/>
+ <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/>
+ <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack"/>
<reg32 offset="0x9304" name="VPC_CNTL_0">
<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
<bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
</reg32>
- <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
- <doc>
- vertex shader
+ <bitset name="a6xx_xs_out_cntl" inline="yes">
+ <doc>
num of varyings plus four for gl_Position (plus one if gl_PointSize)
plus # of transform-feedback (streamout) varyings if using the
hw streamout (rather than stg instructions in shader)
</doc>
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="PSIZE" pos="8" type="boolean"/>
- </reg32>
-
- <reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
- <doc>
- geometry shader
- </doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
- <bitfield name="PSIZE" pos="8" type="boolean"/>
+ <!-- layer / primitiveid only for GS (apparently) -->
<bitfield name="LAYER" pos="9" type="boolean"/>
<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
- </reg32>
-
- <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
- <doc>
- hull shader?
+ <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
+ </bitset>
- num of varyings plus four for gl_Position (plus one if gl_PointSize)
- plus # of transform-feedback (streamout) varyings if using the
- hw streamout (rather than stg instructions in shader)
- </doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
- <bitfield name="PSIZE" pos="8" type="boolean"/>
- </reg32>
- <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
- <doc>
- domain shader
- num of varyings plus four for gl_Position (plus one if gl_PointSize)
- plus # of transform-feedback (streamout) varyings if using the
- hw streamout (rather than stg instructions in shader)
- </doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
- <bitfield name="PSIZE" pos="8" type="boolean"/>
- </reg32>
+ <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
+ <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
+ <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3"/>
+ <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
<doc>
bit N corresponds to brac.N
-->
</reg32>
- <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
+ <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL">
<!-- # of VS outputs including pos/psize -->
- <bitfield name="VSOUT" low="0" high="5" type="uint"/>
+ <bitfield name="OUT" low="0" high="5" type="uint"/>
</reg32>
<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
<reg32 offset="0x0" name="REG">
<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
<!-- # of DS outputs including pos/psize -->
- <bitfield name="DSOUT" low="0" high="4" type="uint"/>
+ <bitfield name="OUT" low="0" high="5" type="uint"/>
</reg32>
<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
<reg32 offset="0x0" name="REG">
-->
</reg32>
- <reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
+ <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL">
<!-- # of VS outputs including pos/psize -->
- <bitfield name="GSOUT" low="0" high="5" type="uint"/>
+ <bitfield name="OUT" low="0" high="5" type="uint"/>
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
</reg32>
.vp_xform_disable = 1,
.vp_clip_code_ignore = 1,
.clip_disable = 1),
- A6XX_GRAS_UNKNOWN_8001(0));
+ A6XX_GRAS_VS_CL_CNTL(0));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_CNTL()); // XXX msaa enable?
tu_cs_emit_regs(cs,
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
+ tu_cs_emit_write_reg(cs, REG_A6XX_VPC_VS_LAYER_CNTL, 0x0000ffff);
/* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
+ tu_cs_emit_write_reg(cs, REG_A6XX_VPC_VS_CLIP_CNTL, 0xffff00);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236,
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
+ tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
A6XX_VPC_CNTL_0_UNKLOC(0xff));
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
- A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VS_PACK, 1);
+ tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
if (hs) {
shader_info *hs_info = &hs->shader->nir->info;
A6XX_PC_TESS_CNTL_OUTPUT(output));
/* xxx: Misc tess unknowns: */
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9103, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
tu_cs_emit(cs, 0x00ffff00);
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9106, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
tu_cs_emit(cs, 0x0000ffff);
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809D, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
tu_cs_emit(cs, 0x0);
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8002, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DS_CL_CNTL, 1);
tu_cs_emit(cs, 0x0);
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
- A6XX_VPC_PACK_PSIZELOC(255) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VS_PACK, 1);
+ tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(255) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_3, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_3_POSITIONLOC(position_loc) |
- A6XX_VPC_PACK_3_PSIZELOC(pointsize_loc) |
- A6XX_VPC_PACK_3_STRIDE_IN_VPC(linkage.max_loc));
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_DS_PACK, 1);
+ tu_cs_emit(cs, A6XX_VPC_DS_PACK_POSITIONLOC(position_loc) |
+ A6XX_VPC_DS_PACK_PSIZELOC(pointsize_loc) |
+ A6XX_VPC_DS_PACK_STRIDE_IN_VPC(linkage.max_loc));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
- tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(linkage.cnt));
+ tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(linkage.cnt));
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
- tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(linkage.max_loc) |
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_DS_OUT_CNTL, 1);
+ tu_cs_emit(cs, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
CONDREG(pointsize_regid, 0x100));
tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
uint32_t primitive_regid =
ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
- A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
- A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_PACK, 1);
+ tu_cs_emit(cs, A6XX_VPC_GS_PACK_POSITIONLOC(position_loc) |
+ A6XX_VPC_GS_PACK_PSIZELOC(pointsize_loc) |
+ A6XX_VPC_GS_PACK_STRIDE_IN_VPC(linkage.max_loc));
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
- tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
+ tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
tu_cs_emit(cs, CONDREG(layer_regid,
- A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
+ A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
uint32_t flags_regid = ir3_find_output_regid(gs,
VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
- tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
- A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
+ tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
+ tu_cs_emit(cs, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
+ A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
- tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
- CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
- CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
- CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_GS_OUT_CNTL, 1);
+ tu_cs_emit(cs, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
+ CONDREG(pointsize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
+ CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
+ CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID));
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
tu_cs_emit(cs,
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
tu_cs_emit(cs, 0);
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_GS_CL_CNTL, 1);
tu_cs_emit(cs, 0);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
tu_cs_emit(cs, 0xff);
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
tu_cs_emit(cs, 0xffff00);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
tu_cs_emit(cs, vs->output_size);
}
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
- tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
+ tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
+ tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt));
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
- tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
- (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_VS_OUT_CNTL, 1);
+ tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
+ (last_shader->writes_psize ? A6XX_PC_VS_OUT_CNTL_PSIZE : 0));
}
static int
A6XX_PC_POLYGON_MODE(.mode = mode));
/* move to hw ctx init? */
- tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001());
+ tu_cs_emit_regs(&cs, A6XX_GRAS_VS_CL_CNTL());
tu_cs_emit_regs(&cs,
A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
A6XX_GRAS_SU_POINT_SIZE(1.0f));
WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
- WRITE(REG_A6XX_GRAS_UNKNOWN_809B, 0);
+ WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
A6XX_PC_TESS_CNTL_OUTPUT(output));
- /* xxx: Misc tess unknowns: */
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
OUT_RING(ring, 0x00ffff00);
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0000ffff);
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
+ OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0);
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
+ OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1);
OUT_RING(ring, 0x0);
- OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
- OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_PSIZELOC(255) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(255) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
- OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
- OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc));
OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
- OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
+ OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
+ OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
CONDREG(psize_regid, 0x100));
} else {
OUT_RING(ring, 0);
}
- OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
- OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
+ OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt));
bool enable_varyings = fs->total_in > 0;
A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
A6XX_VPC_CNTL_0_UNKLOC(0xff));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
- CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
+ OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE));
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
OUT_RING(ring, 0); /* XXX */
- OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
OUT_RING(ring, 0x0000ffff); /* XXX */
bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
}
- OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
- OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
if (gs) {
OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
else
fd6_emit_link_map(screen, vs, gs, ring);
- OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
- OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
- A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
- A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1);
+ OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) |
+ A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) |
+ A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
- OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
+ OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
- OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
+ OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
+ OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
- OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
- OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
- A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
+ OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
+ OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) |
+ A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
- OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
- CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
- CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
- CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
+ OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1);
+ OUT_RING(ring, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
+ CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
+ CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
+ CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID));
uint32_t output;
switch (gs->shader->nir->info.gs.output_primitive) {
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
+ OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
OUT_RING(ring, 0xff);
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
OUT_RING(ring, 0xffff00);
const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
OUT_RING(ring, 0);
}
- OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
+ OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
OUT_RING(ring, 0xffff00);
OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
.vp_clip_code_ignore = 1,
.zero_gb_scale_z = cso->clip_halfz
),
- A6XX_GRAS_UNKNOWN_8001());
+ A6XX_GRAS_VS_CL_CNTL());
OUT_REG(ring,
A6XX_GRAS_SU_CNTL(
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