soc_core: fix missing init on main_ram

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 7ba7b49ec46f07a56880eca53d1a4e866688656a..e3f78e0d6e45d567954251edb44ffa0c3e866bda 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -168,7 +168,7 @@ class SoCCore(LiteXSoC):
 
         # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
         if integrated_main_ram_size:
-            self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size)
+            self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size, integrated_main_ram_init)
 
         # Add Identifier
         if ident != "":