PR 10288

        * arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register
        offset or indexed based addressing mode 3.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fe4fd46d248d2d93fc1c29a7cef3e704c38150c6..2cc210464d3c4cbb0e15fcccbe38d92ff7a76947 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2009-07-20  Nick Clifton  <nickc@redhat.com>
+
+       PR 10288
+       * arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register
+       offset or indexed based addressing mode 3.
+
 2009-07-14  Nick Clifton  <nickc@redhat.com>
 
        PR 10288

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5b2899ca0f8b1aada5b97d9ee88237e20ebbc37b..71f976656effc4d646ba6e7439d36499b8090cbe 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1005,8 +1005,10 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15r, %a"},
   {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15r, %a"},
-  {ARM_EXT_V1, 0x000000b0, 0x0e1000f0, "strh%c\t%12-15r, %s"},
-  {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"},
+  {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15r, %s"},
+  {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15r, %s"},
+  {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15r, %s"},
+  {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15r, %s"},
 
   {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
   {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},