foreach_list(node, instructions) {
fs_inst *inst = (fs_inst *)node;
struct brw_reg src[3], dst;
+ unsigned int last_insn_offset = p->next_insn_offset;
if (unlikely(debug_flag))
annotate(brw, annotation, cfg, inst, p->next_insn_offset);
}
dst = brw_reg_from_fs_reg(&inst->dst);
- brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_flag_reg(p, 0, inst->flag_subreg);
}
abort();
}
+
+ if (inst->conditional_mod) {
+ /* Set the conditional modifier on the last instruction we generated.
+ * Also, make sure we only emitted one instruction - anything else
+ * doesn't make sense.
+ */
+ assert(p->next_insn_offset == last_insn_offset + 16);
+ struct brw_instruction *last = &p->store[last_insn_offset / 16];
+ last->header.destreg__conditionalmod = inst->conditional_mod;
+ }
}
brw_set_uip_jip(p);
}
dst = inst->get_dst();
- brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
generate_vec4_instruction(inst, dst, src);
- if (inst->no_dd_clear || inst->no_dd_check) {
+ if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
assert(p->nr_insn == pre_emit_nr_insn + 1 ||
- !"no_dd_check or no_dd_clear set for IR emitting more "
- "than 1 instruction");
+ !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
+ "emitting more than 1 instruction");
struct brw_instruction *last = &p->store[pre_emit_nr_insn];
+ if (inst->conditional_mod)
+ last->header.destreg__conditionalmod = inst->conditional_mod;
if (inst->no_dd_clear)
last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
if (inst->no_dd_check)