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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 20:39:25 +0000 (21:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 20:41:00 +0000 (21:41 +0100)
libresoc/core.py patch | blob | history

diff --git a/libresoc/core.py b/libresoc/core.py
index 2035df2a32e986b78d351df58734d8ecf593ec34..5e6c02a205e86bd09653bd966d940d6f7a0a1709 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -275,7 +275,7 @@ class LibreSoC(CPU):
             self.pll_ana_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
-            self.cpu_params['o_vco_test_ana_o'] = self.pll_ana_o
+            self.cpu_params['o_vco_test_ana'] = self.pll_ana_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))