MEM: Prepare mport for master/slave split

This patch simplifies the mport in preparation for a split into a
master and slave role for the message ports. In particular,
sendMessageAtomic was only used in a single location and similarly so
sendMessageTiming. The affected interrupt device is updated
accordingly.

diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc
index 23ec20b9a07f3fefd86b14a0c2f008918bdcdfc9..bcfab5fe4885349f877efeb1b93279da59ee45e3 100644 (file)
--- a/src/dev/x86/intdev.cc
+++ b/src/dev/x86/intdev.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2008 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -31,17 +43,21 @@
 #include "dev/x86/intdev.hh"
 
 void
-X86ISA::IntDev::IntPort::sendMessage(ApicList apics,
-        TriggerIntMessage message, bool timing)
+X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message,
+                                     bool timing)
 {
     ApicList::iterator apicIt;
     for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
         PacketPtr pkt = buildIntRequest(*apicIt, message);
         if (timing) {
-            sendMessageTiming(pkt, latency);
+            schedSendTiming(pkt, curTick() + latency);
             // The target handles cleaning up the packet in timing mode.
         } else {
-            sendMessageAtomic(pkt);
+            // ignore the latency involved in the atomic transaction
+            sendAtomic(pkt);
+            assert(pkt->isResponse());
+            // also ignore the latency in handling the response
+            recvResponse(pkt);
             delete pkt->req;
             delete pkt;
         }

diff --git a/src/mem/mport.cc b/src/mem/mport.cc
index 80393c81e96fa654f8cb7137a9ca30f107e55ca5..2c57030b1b9cd0d0821c538be7f0dd88d067fdb4 100644 (file)
--- a/src/mem/mport.cc
+++ b/src/mem/mport.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2008 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -34,30 +46,14 @@ Tick
 MessagePort::recvAtomic(PacketPtr pkt)
 {
     if (pkt->cmd == MemCmd::MessageReq) {
-        // We received a message.
         return recvMessage(pkt);
     } else if (pkt->cmd == MemCmd::MessageResp) {
+        // normally we would never see responses in recvAtomic, but
+        // since the timing port uses recvAtomic to implement
+        // recvTiming we have to deal with both cases
         return recvResponse(pkt);
-    } else if (pkt->wasNacked()) {
-        return recvNack(pkt);
-    } else if (pkt->isError()) {
-        panic("Packet is error.\n");
     } else {
-        panic("Unexpected memory command %s.\n", pkt->cmd.toString());
+        panic("%s received unexpected atomic command %s from %s.\n",
+              name(), pkt->cmd.toString(), getPeer()->name());
     }
 }
-
-void
-MessagePort::sendMessageTiming(PacketPtr pkt, Tick latency)
-{
-    schedSendTiming(pkt, curTick() + latency);
-}
-
-Tick
-MessagePort::sendMessageAtomic(PacketPtr pkt)
-{
-    Tick latency = sendAtomic(pkt);
-    assert(pkt->isResponse());
-    latency += recvResponse(pkt);
-    return latency;
-}

diff --git a/src/mem/mport.hh b/src/mem/mport.hh
index 5975f89f0d3d1ef556388a0af647554103387158..062dcca0b9d88f2f8600925bf476d1e7c8199c2b 100644 (file)
--- a/src/mem/mport.hh
+++ b/src/mem/mport.hh
@@ -59,6 +59,8 @@ class MessagePort : public SimpleTimingPort
 
     Tick recvAtomic(PacketPtr pkt);
 
+  protected:
+
     virtual Tick recvMessage(PacketPtr pkt) = 0;
 
     // Accept and ignore responses.
@@ -66,15 +68,6 @@ class MessagePort : public SimpleTimingPort
     {
         return 0;
     }
-
-    // Since by default we're assuming everything we send is accepted, panic.
-    virtual Tick recvNack(PacketPtr pkt)
-    {
-        panic("Unhandled message nack.\n");
-    }
-
-    void sendMessageTiming(PacketPtr pkt, Tick latency);
-    Tick sendMessageAtomic(PacketPtr pkt);
 };
 
 #endif