* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
-#define __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
+#ifndef __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
+#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
// For Addr type.
#include "arch/alpha/isa_traits.hh"
unsigned indexMask;
};
-#endif // __CPU_BETA_CPU_2BIT_LOCAL_PRED_HH__
+#endif // __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
// Todo: Find all the stuff in ExecContext and ev5 that needs to be
// specifically designed for this CPU.
-#ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
-#define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
+#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
+#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
#include "cpu/o3/cpu.hh"
template <class Impl>
-class AlphaFullCPU : public FullBetaCPU<Impl>
+class AlphaFullCPU : public FullO3CPU<Impl>
{
public:
typedef typename Impl::ISA AlphaISA;
};
-#endif // __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
+#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#include "base/cprintf.hh"
#include "base/statistics.hh"
template <class Impl>
AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
- : FullBetaCPU<Impl>(params)
+ : FullO3CPU<Impl>(params)
{
DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
-#define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
+#ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__
+#define __CPU_O3_CPU_ALPHA_DYN_INST_HH__
#include "cpu/base_dyn_inst.hh"
#include "cpu/o3/alpha_cpu.hh"
}
};
-#endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
+#endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_ALPHA_IMPL_HH__
-#define __CPU_BETA_CPU_ALPHA_IMPL_HH__
+#ifndef __CPU_O3_CPU_ALPHA_IMPL_HH__
+#define __CPU_O3_CPU_ALPHA_IMPL_HH__
#include "arch/alpha/isa_traits.hh"
};
};
-#endif // __CPU_BETA_CPU_ALPHA_IMPL_HH__
+#endif // __CPU_O3_CPU_ALPHA_IMPL_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
-#define __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
+#ifndef __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
+#define __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
#include "cpu/o3/cpu.hh"
bool defReg;
};
-#endif // __CPU_BETA_CPU_ALPHA_PARAMS_HH__
+#endif // __CPU_O3_CPU_ALPHA_PARAMS_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_BTB_HH__
-#define __CPU_BETA_CPU_BTB_HH__
+#ifndef __CPU_O3_CPU_BTB_HH__
+#define __CPU_O3_CPU_BTB_HH__
// For Addr type.
#include "arch/alpha/isa_traits.hh"
unsigned tagShiftAmt;
};
-#endif // __CPU_BETA_CPU_BTB_HH__
+#endif // __CPU_O3_CPU_BTB_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_COMM_HH__
-#define __CPU_BETA_CPU_COMM_HH__
+#ifndef __CPU_O3_CPU_COMM_HH__
+#define __CPU_O3_CPU_COMM_HH__
#include <vector>
commitComm commitInfo;
};
-#endif //__CPU_BETA_CPU_COMM_HH__
+#endif //__CPU_O3_CPU_COMM_HH__
// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
// have the original function handle writing to the IPR register.
-#ifndef __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
-#define __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
+#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
+#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
#include "base/statistics.hh"
#include "base/timebuf.hh"
Stats::Distribution<> n_committed_dist;
};
-#endif // __CPU_BETA_CPU_SIMPLE_COMMIT_HH__
+#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
}
template <class Impl>
-FullBetaCPU<Impl>::TickEvent::TickEvent(FullBetaCPU<Impl> *c)
+FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
{
}
template <class Impl>
void
-FullBetaCPU<Impl>::TickEvent::process()
+FullO3CPU<Impl>::TickEvent::process()
{
cpu->tick();
}
template <class Impl>
const char *
-FullBetaCPU<Impl>::TickEvent::description()
+FullO3CPU<Impl>::TickEvent::description()
{
- return "FullBetaCPU tick event";
+ return "FullO3CPU tick event";
}
//Call constructor to all the pipeline stages here
template <class Impl>
-FullBetaCPU<Impl>::FullBetaCPU(Params ¶ms)
+FullO3CPU<Impl>::FullO3CPU(Params ¶ms)
#ifdef FULL_SYSTEM
: BaseFullCPU(params),
#else
// The stages also need their CPU pointer setup. However this must be
// done at the upper level CPU because they have pointers to the upper
- // level CPU, and not this FullBetaCPU.
+ // level CPU, and not this FullO3CPU.
// Give each of the stages the time buffer they will use.
fetch.setTimeBuffer(&timeBuffer);
}
template <class Impl>
-FullBetaCPU<Impl>::~FullBetaCPU()
+FullO3CPU<Impl>::~FullO3CPU()
{
}
template <class Impl>
void
-FullBetaCPU<Impl>::fullCPURegStats()
+FullO3CPU<Impl>::fullCPURegStats()
{
// Register any of the FullCPU's stats here.
}
template <class Impl>
void
-FullBetaCPU<Impl>::tick()
+FullO3CPU<Impl>::tick()
{
- DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullBetaCPU.\n");
+ DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
//Tick each of the stages if they're actually running.
//Will want to figure out a way to unschedule itself if they're all
template <class Impl>
void
-FullBetaCPU<Impl>::init()
+FullO3CPU<Impl>::init()
{
if(!deferRegistration)
{
template <class Impl>
void
-FullBetaCPU<Impl>::activateContext(int thread_num, int delay)
+FullO3CPU<Impl>::activateContext(int thread_num, int delay)
{
// Needs to set each stage to running as well.
template <class Impl>
void
-FullBetaCPU<Impl>::suspendContext(int thread_num)
+FullO3CPU<Impl>::suspendContext(int thread_num)
{
panic("suspendContext unimplemented!");
}
template <class Impl>
void
-FullBetaCPU<Impl>::deallocateContext(int thread_num)
+FullO3CPU<Impl>::deallocateContext(int thread_num)
{
panic("deallocateContext unimplemented!");
}
template <class Impl>
void
-FullBetaCPU<Impl>::haltContext(int thread_num)
+FullO3CPU<Impl>::haltContext(int thread_num)
{
panic("haltContext unimplemented!");
}
template <class Impl>
void
-FullBetaCPU<Impl>::switchOut()
+FullO3CPU<Impl>::switchOut()
{
- panic("FullBetaCPU does not have a switch out function.\n");
+ panic("FullO3CPU does not have a switch out function.\n");
}
template <class Impl>
void
-FullBetaCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
+FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
{
BaseCPU::takeOverFrom(oldCPU);
template <class Impl>
InstSeqNum
-FullBetaCPU<Impl>::getAndIncrementInstSeq()
+FullO3CPU<Impl>::getAndIncrementInstSeq()
{
// Hopefully this works right.
return globalSeqNum++;
template <class Impl>
uint64_t
-FullBetaCPU<Impl>::readIntReg(int reg_idx)
+FullO3CPU<Impl>::readIntReg(int reg_idx)
{
return regFile.readIntReg(reg_idx);
}
template <class Impl>
float
-FullBetaCPU<Impl>::readFloatRegSingle(int reg_idx)
+FullO3CPU<Impl>::readFloatRegSingle(int reg_idx)
{
return regFile.readFloatRegSingle(reg_idx);
}
template <class Impl>
double
-FullBetaCPU<Impl>::readFloatRegDouble(int reg_idx)
+FullO3CPU<Impl>::readFloatRegDouble(int reg_idx)
{
return regFile.readFloatRegDouble(reg_idx);
}
template <class Impl>
uint64_t
-FullBetaCPU<Impl>::readFloatRegInt(int reg_idx)
+FullO3CPU<Impl>::readFloatRegInt(int reg_idx)
{
return regFile.readFloatRegInt(reg_idx);
}
template <class Impl>
void
-FullBetaCPU<Impl>::setIntReg(int reg_idx, uint64_t val)
+FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
{
regFile.setIntReg(reg_idx, val);
}
template <class Impl>
void
-FullBetaCPU<Impl>::setFloatRegSingle(int reg_idx, float val)
+FullO3CPU<Impl>::setFloatRegSingle(int reg_idx, float val)
{
regFile.setFloatRegSingle(reg_idx, val);
}
template <class Impl>
void
-FullBetaCPU<Impl>::setFloatRegDouble(int reg_idx, double val)
+FullO3CPU<Impl>::setFloatRegDouble(int reg_idx, double val)
{
regFile.setFloatRegDouble(reg_idx, val);
}
template <class Impl>
void
-FullBetaCPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
+FullO3CPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val)
{
regFile.setFloatRegInt(reg_idx, val);
}
template <class Impl>
uint64_t
-FullBetaCPU<Impl>::readPC()
+FullO3CPU<Impl>::readPC()
{
return regFile.readPC();
}
template <class Impl>
void
-FullBetaCPU<Impl>::setNextPC(uint64_t val)
+FullO3CPU<Impl>::setNextPC(uint64_t val)
{
regFile.setNextPC(val);
}
template <class Impl>
void
-FullBetaCPU<Impl>::setPC(Addr new_PC)
+FullO3CPU<Impl>::setPC(Addr new_PC)
{
regFile.setPC(new_PC);
}
template <class Impl>
void
-FullBetaCPU<Impl>::addInst(DynInstPtr &inst)
+FullO3CPU<Impl>::addInst(DynInstPtr &inst)
{
instList.push_back(inst);
}
template <class Impl>
void
-FullBetaCPU<Impl>::instDone()
+FullO3CPU<Impl>::instDone()
{
// Keep an instruction count.
numInsts++;
template <class Impl>
void
-FullBetaCPU<Impl>::removeBackInst(DynInstPtr &inst)
+FullO3CPU<Impl>::removeBackInst(DynInstPtr &inst)
{
DynInstPtr inst_to_delete;
template <class Impl>
void
-FullBetaCPU<Impl>::removeFrontInst(DynInstPtr &inst)
+FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
{
DynInstPtr inst_to_remove;
template <class Impl>
void
-FullBetaCPU<Impl>::removeInstsNotInROB()
+FullO3CPU<Impl>::removeInstsNotInROB()
{
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
"list.\n");
template <class Impl>
void
-FullBetaCPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
+FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
{
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
"list.\n");
template <class Impl>
void
-FullBetaCPU<Impl>::removeAllInsts()
+FullO3CPU<Impl>::removeAllInsts()
{
instList.clear();
}
template <class Impl>
void
-FullBetaCPU<Impl>::dumpInsts()
+FullO3CPU<Impl>::dumpInsts()
{
int num = 0;
typename list<DynInstPtr>::iterator inst_list_it = instList.begin();
template <class Impl>
void
-FullBetaCPU<Impl>::wakeDependents(DynInstPtr &inst)
+FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
{
iew.wakeDependents(inst);
}
-// Forward declaration of FullBetaCPU.
-template class Full
BetaCPU<AlphaSimpleImpl>;
+// Forward declaration of FullO3CPU.
+template class Full
O3CPU<AlphaSimpleImpl>;
//itself properly. Threads!
// Avoid running stages and advancing queues if idle/stalled.
-#ifndef __CPU_BETA_CPU_FULL_CPU_HH__
-#define __CPU_BETA_CPU_FULL_CPU_HH__
+#ifndef __CPU_O3_CPU_FULL_CPU_HH__
+#define __CPU_O3_CPU_FULL_CPU_HH__
#include <iostream>
#include <list>
};
template <class Impl>
-class FullBetaCPU : public BaseFullCPU
+class FullO3CPU : public BaseFullCPU
{
public:
//Put typedefs from the Impl here.
class TickEvent : public Event
{
private:
- FullBetaCPU<Impl> *cpu;
+ FullO3CPU<Impl> *cpu;
public:
- TickEvent(FullBetaCPU<Impl> *c);
+ TickEvent(FullO3CPU<Impl> *c);
void process();
const char *description();
};
}
public:
- FullBetaCPU(Params ¶ms);
- ~FullBetaCPU();
+ FullO3CPU(Params ¶ms);
+ ~FullO3CPU();
void fullCPURegStats();
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_CPU_POLICY_HH__
-#define __CPU_BETA_CPU_CPU_POLICY_HH__
+#ifndef __CPU_O3_CPU_CPU_POLICY_HH__
+#define __CPU_O3_CPU_CPU_POLICY_HH__
#include "cpu/o3/bpred_unit.hh"
#include "cpu/o3/free_list.hh"
};
-#endif //__CPU_BETA_CPU_CPU_POLICY_HH__
+#endif //__CPU_O3_CPU_CPU_POLICY_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
-#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
+#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
+#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
#include <queue>
Stats::Scalar<> decodeSquashedInsts;
};
-#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__
+#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
// Todo: SMT fetch,
// Add a way to get a stage's current status.
-#ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__
-#define __CPU_BETA_CPU_SIMPLE_FETCH_HH__
+#ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
+#define __CPU_O3_CPU_SIMPLE_FETCH_HH__
#include "base/statistics.hh"
#include "base/timebuf.hh"
Stats::Distribution<> fetch_nisn_dist;
};
-#endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__
+#endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_FREE_LIST_HH__
-#define __CPU_BETA_CPU_FREE_LIST_HH__
+#ifndef __CPU_O3_CPU_FREE_LIST_HH__
+#define __CPU_O3_CPU_FREE_LIST_HH__
#include <iostream>
#include <queue>
freeFloatRegs.push(freed_reg);
}
-#endif // __CPU_BETA_CPU_FREE_LIST_HH__
+#endif // __CPU_O3_CPU_FREE_LIST_HH__
//Need to handle delaying writes to the writeback bus if it's full at the
//given time.
-#ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__
-#define __CPU_BETA_CPU_SIMPLE_IEW_HH__
+#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
+#define __CPU_O3_CPU_SIMPLE_IEW_HH__
#include <queue>
Stats::Scalar<> predictedTakenIncorrect;
};
-#endif // __CPU_BETA_CPU_IEW_HH__
+#endif // __CPU_O3_CPU_IEW_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_INST_QUEUE_HH__
-#define __CPU_BETA_CPU_INST_QUEUE_HH__
+#ifndef __CPU_O3_CPU_INST_QUEUE_HH__
+#define __CPU_O3_CPU_INST_QUEUE_HH__
#include <list>
#include <map>
};
-#endif //__CPU_BETA_CPU_INST_QUEUE_HH__
+#endif //__CPU_O3_CPU_INST_QUEUE_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_MEM_DEP_UNIT_HH__
-#define __CPU_BETA_CPU_MEM_DEP_UNIT_HH__
+#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__
+#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__
#include <map>
#include <set>
Stats::Scalar<> conflictingStores;
};
-#endif // __CPU_BETA_CPU_MEM_DEP_UNIT_HH__
+#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_RAS_HH__
-#define __CPU_BETA_CPU_RAS_HH__
+#ifndef __CPU_O3_CPU_RAS_HH__
+#define __CPU_O3_CPU_RAS_HH__
// For Addr type.
#include "arch/alpha/isa_traits.hh"
unsigned tos;
};
-#endif // __CPU_BETA_CPU_RAS_HH__
+#endif // __CPU_O3_CPU_RAS_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_REGFILE_HH__
-#define __CPU_BETA_CPU_REGFILE_HH__
+#ifndef __CPU_O3_CPU_REGFILE_HH__
+#define __CPU_O3_CPU_REGFILE_HH__
// @todo: Destructor
#endif // #ifdef FULL_SYSTEM
-#endif // __CPU_BETA_CPU_REGFILE_HH__
+#endif // __CPU_O3_CPU_REGFILE_HH__
// May want to have different statuses to differentiate the different stall
// conditions.
-#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__
-#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__
+#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
+#define __CPU_O3_CPU_SIMPLE_RENAME_HH__
#include <list>
Stats::Scalar<> renameValidUndoneMaps;
};
-#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__
+#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
// Have it so that there's a more meaningful name given to the variable
// that marks the beginning of the FP registers.
-#ifndef __CPU_BETA_CPU_RENAME_MAP_HH__
-#define __CPU_BETA_CPU_RENAME_MAP_HH__
+#ifndef __CPU_O3_CPU_RENAME_MAP_HH__
+#define __CPU_O3_CPU_RENAME_MAP_HH__
#include <iostream>
#include <utility>
std::vector<bool> miscScoreboard;
};
-#endif //__CPU_BETA_CPU_RENAME_MAP_HH__
+#endif //__CPU_O3_CPU_RENAME_MAP_HH__
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#include "cpu/o3/alpha_dyn_inst.hh"
#include "cpu/o3/alpha_impl.hh"
// all instructions after the instruction, and all instructions after *and*
// including that instruction.
-#ifndef __CPU_BETA_CPU_ROB_HH__
-#define __CPU_BETA_CPU_ROB_HH__
+#ifndef __CPU_O3_CPU_ROB_HH__
+#define __CPU_O3_CPU_ROB_HH__
#include <utility>
#include <vector>
bool doneSquashing;
};
-#endif //__CPU_BETA_CPU_ROB_HH__
+#endif //__CPU_O3_CPU_ROB_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_ROB_IMPL_HH__
-#define __CPU_BETA_CPU_ROB_IMPL_HH__
+#ifndef __CPU_O3_CPU_ROB_IMPL_HH__
+#define __CPU_O3_CPU_ROB_IMPL_HH__
#include "cpu/o3/rob.hh"
return (*tail)->seqNum;
}
-#endif // __CPU_BETA_CPU_ROB_IMPL_HH__
+#endif // __CPU_O3_CPU_ROB_IMPL_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_SAT_COUNTER_HH__
-#define __CPU_BETA_CPU_SAT_COUNTER_HH__
+#ifndef __CPU_O3_CPU_SAT_COUNTER_HH__
+#define __CPU_O3_CPU_SAT_COUNTER_HH__
#include "sim/host.hh"
uint8_t counter;
};
-#endif // __CPU_BETA_CPU_SAT_COUNTER_HH__
+#endif // __CPU_O3_CPU_SAT_COUNTER_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_STORE_SET_HH__
-#define __CPU_BETA_CPU_STORE_SET_HH__
+#ifndef __CPU_O3_CPU_STORE_SET_HH__
+#define __CPU_O3_CPU_STORE_SET_HH__
#include <vector>
int offset_bits;
};
-#endif // __CPU_BETA_CPU_STORE_SET_HH__
+#endif // __CPU_O3_CPU_STORE_SET_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
-#define __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
+#ifndef __CPU_O3_CPU_TOURNAMENT_PRED_HH__
+#define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
// For Addr type.
#include "arch/alpha/isa_traits.hh"
unsigned threshold;
};
-#endif // __CPU_BETA_CPU_TOURNAMENT_PRED_HH__
+#endif // __CPU_O3_CPU_TOURNAMENT_PRED_HH__
<hr size="1"><address style="align: right;"><small>
Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
-<address><a href="mailto:m5-dev@eecs.umich.edu">M5 Development Team</a></address>
</body>
</html>
projects / gem5.git / commitdiff