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radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Sun, 19 Nov 2017 14:24:28 +0000 (15:24 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 3 Jul 2019 19:51:12 +0000 (15:51 -0400)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/gallium/drivers/radeonsi/si_state.c patch | blob | history

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 4d76e13e52710eadcda4027499b6273395020291..0044353fd66e93f029b2879d207f09610079f4c7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5456,7 +5456,11 @@ static void si_init_config(struct si_context *sctx)
                si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
        }
 
-       if (sctx->chip_class >= GFX9) {
+       if (sctx->chip_class >= GFX10) {
+               si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
+               si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
+               si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
+       } else if (sctx->chip_class >= GFX9) {
                si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
                si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
                si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);