i965/fs: Implement FS_OPCODE_SET_OMASK on Broadwell.

I made a few changes which I think simplify the code a bit compared to
the Gen7 implementation, but which are largely pointless.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index fd828f4d90412a9e4db78a62a1f8b7d19db9ce9c..8a596bcaa0e4b1de81f0821b8cb96d83c2880e6e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -720,6 +720,9 @@ private:
                                             struct brw_reg index,
                                             struct brw_reg offset);
    void generate_mov_dispatch_to_flags(fs_inst *ir);
+   void generate_set_omask(fs_inst *ir,
+                           struct brw_reg dst,
+                           struct brw_reg sample_mask);
    void generate_set_sample_id(fs_inst *ir,
                                struct brw_reg dst,
                                struct brw_reg src0,

diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
index dd067954e45e44ccde6586f1218a646e9b6f8ab4..de19bd28b752cfa8188a9080b2760fa857d3800e 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
@@ -596,6 +596,40 @@ gen8_fs_generator::generate_set_simd4x2_offset(fs_inst *ir,
    MOV_RAW(retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
 }
 
+/**
+ * Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
+ * (when mask is passed as a uniform) of register mask before moving it
+ * to register dst.
+ */
+void
+gen8_fs_generator::generate_set_omask(fs_inst *inst,
+                                      struct brw_reg dst,
+                                      struct brw_reg mask)
+{
+   assert(dst.type == BRW_REGISTER_TYPE_UW);
+
+   if (dispatch_width == 16)
+      dst = vec16(dst);
+
+   if (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
+       mask.width == BRW_WIDTH_8 &&
+       mask.hstride == BRW_HORIZONTAL_STRIDE_1) {
+      mask = stride(mask, 16, 8, 2);
+   } else {
+      assert(mask.vstride == BRW_VERTICAL_STRIDE_0 &&
+             mask.width == BRW_WIDTH_1 &&
+             mask.hstride == BRW_HORIZONTAL_STRIDE_0);
+   }
+
+   unsigned save_exec_size = default_state.exec_size;
+   default_state.exec_size = BRW_EXECUTE_8;
+
+   gen8_instruction *mov = MOV(dst, retype(mask, dst.type));
+   gen8_set_mask_control(mov, BRW_MASK_DISABLE);
+
+   default_state.exec_size = save_exec_size;
+}
+
 /**
  * Do a special ADD with vstride=1, width=4, hstride=0 for src1.
  */
@@ -998,7 +1032,7 @@ gen8_fs_generator::generate_code(exec_list *instructions)
          break;
 
       case FS_OPCODE_SET_OMASK:
-         assert(!"XXX: Missing Gen8 scalar support for SET_OMASK");
+         generate_set_omask(ir, dst, src[0]);
          break;
 
       case FS_OPCODE_SET_SAMPLE_ID: