Retry on fixing TODOs

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 8a2c2caf53fdd799d0622b87b764d971732f0c31..dbc3f74550cb65a17b60e431bc2ed793ada6a1d0 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -100,14 +100,10 @@ code sigA sigB sigC sigD sigM clock
                        sigM.append(P[i]);
                }
                log_assert(nusers(P.extract_end(i)) <= 1);
+               log_assert(!sigM.empty());
        }
        else
                sigM = P;
-       // TODO: Check if necessary
-       // This sigM could have no users if downstream $add
-       //   is narrower than $mul result, for example
-       if (sigM.empty())
-               reject;
 
        clock = port(dsp, \CLK, SigBit());
 endcode
@@ -160,12 +156,9 @@ match preAdd
 endmatch
 
 code sigA sigD
-       // TODO: Check if this is necessary?
        if (preAdd) {
                sigA = port(preAdd, \A);
                sigD = port(preAdd, \B);
-               if (GetSize(sigA) < GetSize(sigD))
-                       std::swap(sigA, sigD);
        }
 endcode
 

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index b87a686a15906f67d063d85e3d8db0ebe7de4172..3d911b4783c00518b9eac0c0db675db6ac73c426 100644 (file)
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -79,11 +79,6 @@ endcode
 //     (attached to at most two $mux cells that implement clock-enable or
 //      reset functionality, using the in_dffe subpattern)
 code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
-       // TODO: Any downside to allowing this?
-       // If this DSP implements an accumulator, do not attempt to match
-       if (sigC == sigP)
-               reject;
-
        argQ = sigC;
        subpattern(in_dffe);
        if (dff) {