core/spi: make cs_n optional (sometimes managed externally)

diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py
index 64c200029b80f862e38bbdaf97da627d6cfdb1f5..bf12cd15390f99ba0b7655e291a46e7f7234bfe4 100644 (file)
--- a/litex/soc/cores/spi.py
+++ b/litex/soc/cores/spi.py
@@ -30,7 +30,8 @@ class SPIMaster(Module, AutoCSR):
         self._status  = CSRStatus(1)
         self._mosi    = CSRStorage(data_width)
         self._miso    = CSRStatus(data_width)
-        self._cs      = CSRStorage(len(pads.cs_n), reset=1)
+        if hasattr(pads, "cs_n"):
+            self._cs      = CSRStorage(len(pads.cs_n), reset=1)
 
         self.irq = Signal()
 
@@ -101,8 +102,9 @@ class SPIMaster(Module, AutoCSR):
         )
 
         # Chip Select generation -------------------------------------------------------------------
-        for i in range(len(pads.cs_n)):
-            self.comb += pads.cs_n[i].eq(~self._cs.storage[i] | ~cs)
+        if hasattr(pads, "cs_n"):
+            for i in range(len(pads.cs_n)):
+                self.comb += pads.cs_n[i].eq(~self._cs.storage[i] | ~cs)
 
         # Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) ---------------
         mosi_data = Signal(data_width)