add 256-bit packed SIMD emulation table

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index b53a53e7a4e20496a4356f1d5eaabfd22a4008fa..a5a8f8ea767c41862fb739c15b82371c7d7d5295 100644 (file)
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -364,3 +364,16 @@ Then, all 128-bit packed SIMD types can be emulated without additional `setvl` i
 | `f16x8`                      | sv.fadd/subvl=2/elwid=16 FRT.vector, FRA.vector, FRB.vector |
 | `f32x4`                      | sv.fadd/elwid=32 FRT.vector, FRA.vector, FRB.vector         |
 | `f64x2`                      | sv.fadd/subvl=2 FRT.scalar, FRA.scalar, FRB.scalar          |
+
+Likewise, all 256-bit packed SIMD types can be emulated without additional `setvl` instructions by setting VL=8 on entry to the code:
+
+| 256-bit SIMD type             | SVP64 vector add                                            |
+|-------------------------------|-------------------------------------------------------------|
+| `u8x32`/`i8x32`               | sv.add/subvl=4/elwid=8 RT.vector, RA.vector, RB.vector      |
+| `u16x16`/`i16x16`             | sv.add/subvl=2/elwid=16 RT.vector, RA.vector, RB.vector     |
+| `u32x8`/`i32x8`               | sv.add/elwid=32 RT.vector, RA.vector, RB.vector             |
+| `u64x4`/`i64x4`               | sv.add/subvl=4 RT.scalar, RA.scalar, RB.scalar              |
+| `bf16x16` (not in base SVP64) | sv.fadd/subvl=2/elwid=8 FRT.vector, FRA.vector, FRB.vector  |
+| `f16x16`                      | sv.fadd/subvl=2/elwid=16 FRT.vector, FRA.vector, FRB.vector |
+| `f32x8`                       | sv.fadd/elwid=32 FRT.vector, FRA.vector, FRB.vector         |
+| `f64x4`                       | sv.fadd/subvl=4 FRT.scalar, FRA.scalar, FRB.scalar          |