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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index cd106f01742286230ad87515e4185374c4c17bd8..3aeb658592d47ee78b2633ff55113125c21898b5 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -1,5 +1,3 @@
-[[!tag opf_rfc]]
-  
 # OpenPOWER Foundation External RFC LS001
 
 Links
@@ -237,7 +235,7 @@ Transcendentals are required:
 * QTY 33of X-Form "1-argument" (fsin, fsins, fcos, fcoss)
 * QTY 15of X-Form "2-argument" (pow, atan2, fhypot)
 
---
+[[!tag opf_rfc]]
 
 [^extend]: Prefix opcode space **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2
 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations.