si_pm4_free_state_simple(state);
}
-unsigned si_pm4_dirty_dw(struct si_context *sctx)
-{
- unsigned count = 0;
-
- for (int i = 0; i < NUMBER_OF_STATES; ++i) {
- struct si_pm4_state *state = sctx->queued.array[i];
-
- if (!state || sctx->emitted.array[i] == state)
- continue;
-
- count += state->ndw;
- }
-
- return count;
-}
-
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
{
struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+
for (int i = 0; i < state->nbo; ++i) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
state->bo_usage[i], state->bo_priority[i]);
}
- memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
-
- for (int i = 0; i < state->nrelocs; ++i) {
- cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
- }
-
- cs->cdw += state->ndw;
+ radeon_emit_array(cs, state->pm4, state->ndw);
}
void si_pm4_emit_dirty(struct si_context *sctx)
enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
- /* relocs for shader data */
- unsigned nrelocs;
- unsigned relocs[SI_PM4_MAX_RELOCS];
-
bool compute_pkt;
};
struct si_pm4_state *state,
unsigned idx);
-unsigned si_pm4_dirty_dw(struct si_context *sctx);
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
void si_pm4_emit_dirty(struct si_context *sctx);
void si_pm4_reset_emitted(struct si_context *sctx);