Fix corner case on assertion.

I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 936a9c1fa3cc383692d726282ba7086ffbbfc2c0..e0301a757b3b5bef29e45d4d5c2eae5784cd3a1f 100644 (file)
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -132,7 +132,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt)
                 pkt_data = pkt->getPtr<uint8_t>() + offset;
                 write_data = target->getPtr<uint8_t>();
                 data_size = pkt->getSize() - offset;
-                assert(data_size > pkt->getSize());
+                assert(data_size >= pkt->getSize());
                 if (data_size > target->getSize())
                     data_size = target->getSize();
             }

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d8afcb00955101f37fb07eada0c3227e62bfd258..ea30dbba67d7cb62b9d52426751e05e97a86f0b0 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -585,7 +585,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
                         pkt_data = pkt->getPtr<uint8_t>() + offset;
                         write_data = target->getPtr<uint8_t>();
                         data_size = pkt->getSize() - offset;
-                        assert(data_size > pkt->getSize());
+                        assert(data_size >= pkt->getSize());
                         if (data_size > target->getSize())
                             data_size = target->getSize();
                     }
@@ -620,7 +620,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
                     pkt_data = pkt->getPtr<uint8_t>() + offset;
                     write_data = write->getPtr<uint8_t>();
                     data_size = pkt->getSize() - offset;
-                    assert(data_size > pkt->getSize());
+                    assert(data_size >= pkt->getSize());
                     if (data_size > write->getSize())
                         data_size = write->getSize();
                 }

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 116e71af64afda1a44d5510a11e94a7633b19a5f..2b990418c45f3a8a912ebce63696ba98f4a27458 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -53,7 +53,7 @@ class L2(BaseCache):
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
-cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ]
+cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
@@ -90,6 +90,6 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
-#root.trace.flags="Cache CachePort Bus"
-#root.trace.cycle=3810800
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1