(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 9ec5bed07585f72beba3761e06e9ea8a9cd0310e..2871bd9bc7618764aa3bb4755b9be1cd7080e5e9 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -970,7 +970,12 @@ What, then, of `sv.madded`? If the destination is hard-coded to
 RT and RT+1 the instruction is not useful when Vectorised because
 the output will be overwritten on the next element.  To solve this
 is easy: define the destination registers as RT and RT+MAXVL
-respectively.
+respectively.  This makes it easy for compilers to statically allocate
+registers even when VL changes dynamically.
+
+Bear in mind that both RT and RT+MAXVL are starting points for Vectors,
+and bear in mind that element-width overrides still have to be taken
+into consideration, 
 
 
 * [[isa/svfixedarith]]