}
/* SHADER SAMPLER R600/R700 */
-static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
{
struct r600_reg r600_shader_sampler[] = {
{R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
}
/* SHADER SAMPLER BORDER EG/CM */
-static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id)
+static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
{
struct r600_reg r600_shader_sampler_border[] = {
{R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0},
return 0;
}
-static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset)
+static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
struct r600_reg r600_loop_consts[32];
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
struct r600_pipe_state *rstate;
- u32 color_control, target_mask;
+ uint32_t color_control, target_mask;
/* FIXME there is more then 8 framebuffer */
unsigned blend_cntl[8];
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 tl, br;
+ uint32_t tl, br;
if (rstate == NULL)
return;
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 shader_mask, tl, br;
+ uint32_t shader_mask, tl, br;
int tl_x, tl_y, br_x, br_y;
if (rstate == NULL)
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
struct winsys_handle;
enum radeon_family {
#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
struct r600_pipe_reg {
- u32 value;
+ uint32_t value;
struct r600_block *block;
struct r600_resource *bo;
enum radeon_bo_usage bo_usage;
- u32 id;
+ uint32_t id;
};
struct r600_pipe_state {
struct r600_pipe_resource_state {
unsigned id;
- u32 val[8];
+ uint32_t val[8];
struct r600_resource *bo[2];
enum radeon_bo_usage bo_usage[2];
};
unsigned pm4_ndwords;
unsigned pm4_flush_ndwords;
unsigned nbo;
- u16 nreg;
- u16 nreg_dirty;
- u32 *reg;
- u32 pm4[R600_BLOCK_MAX_REG];
+ uint16_t nreg;
+ uint16_t nreg_dirty;
+ uint32_t *reg;
+ uint32_t pm4[R600_BLOCK_MAX_REG];
unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
};
unsigned creloc;
struct r600_resource **bo;
- u32 *pm4;
+ uint32_t *pm4;
unsigned pm4_cdwords;
/* The list of active queries. Only one query of each type can be active. */
int num_ps_resources, num_vs_resources, num_fs_resources;
boolean have_depth_texture, have_depth_fb;
- unsigned num_so_targets;
- struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
- boolean streamout_start;
- unsigned streamout_append_bitmask;
- unsigned *vs_so_stride_in_dw;
+ unsigned num_so_targets;
+ struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
+ boolean streamout_start;
+ unsigned streamout_append_bitmask;
+ unsigned *vs_so_stride_in_dw;
};
struct r600_draw {
- u32 vgt_num_indices;
- u32 vgt_num_instances;
- u32 vgt_index_type;
- u32 vgt_draw_initiator;
- u32 indices_bo_offset;
+ uint32_t vgt_num_indices;
+ uint32_t vgt_num_instances;
+ uint32_t vgt_index_type;
+ uint32_t vgt_draw_initiator;
+ uint32_t indices_bo_offset;
unsigned db_render_override;
unsigned db_render_control;
struct r600_resource *indices;
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
- u32 offset, u32 value,
- u32 range_id, u32 block_id,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
struct r600_resource *bo,
enum radeon_bo_usage usage);
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- u32 offset, u32 value,
+ uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage);
#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
- u32 value)
+ uint32_t value)
{
state->regs[state->nregs].value = value;
state->nregs++;
}
static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
- u32 value, struct r600_resource *bo,
+ uint32_t value, struct r600_resource *bo,
enum radeon_bo_usage usage)
{
state->regs[state->nregs].value = value;
return 0;
}
-void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
{
switch(value) {
case 0:
const struct util_format_description *desc;
unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
unsigned format, num_format, format_comp, endian;
- u32 *bytecode;
+ uint32_t *bytecode;
int i, r;
/* Vertex element offsets need special handling. If the offset is
unsigned nstack;
unsigned nresource;
unsigned force_add_cf;
- u32 *bytecode;
- u32 fc_sp;
+ uint32_t *bytecode;
+ uint32_t fc_sp;
struct r600_cf_stack_entry fc_stack[32];
unsigned call_sp;
struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH];
int r600_bytecode_build(struct r600_bytecode *bc);
int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst);
int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type);
-void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg);
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg);
void r600_bytecode_dump(struct r600_bytecode *bc);
int cm_bytecode_add_cf_end(struct r600_bytecode *bc);
void r600_get_backend_mask(struct r600_context *ctx)
{
struct r600_resource *buffer;
- u32 *results;
+ uint32_t *results;
unsigned num_backends = ctx->screen->info.r600_num_backends;
unsigned i, mask = 0;
err:
/* fallback to old method - set num_backends lower bits to 1 */
- ctx->backend_mask = (~((u32)0))>>(32-num_backends);
+ ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
return;
}
}
/* SHADER SAMPLER R600/R700 */
-static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
{
struct r600_reg r600_shader_sampler[] = {
{R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
}
/* SHADER SAMPLER BORDER R600/R700 */
-static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
+static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
{
struct r600_reg r600_shader_sampler_border[] = {
{R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
}
-static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
+static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
struct r600_reg r600_loop_consts[32];
void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
{
unsigned new_results_end, i;
- u32 *results;
+ uint32_t *results;
uint64_t va;
r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
case PIPE_QUERY_OCCLUSION_PREDICATE:
results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
if (results) {
- results = (u32*)((char*)results + query->results_end);
+ results = (uint32_t*)((char*)results + query->results_end);
memset(results, 0, query->result_size);
/* Set top bits for unused backends */
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
- results = (u32*)((char*)results + query->results_end);
+ results = (uint32_t*)((char*)results + query->results_end);
memset(results, 0, query->result_size);
ctx->ws->buffer_unmap(query->buffer->buf);
break;
} else {
unsigned results_base = query->results_start;
unsigned count;
- u32 op;
+ uint32_t op;
/* find count of the query data blocks */
count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0;
/*
* common helpers
*/
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
+static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
{
return value * (1 << frac_bits);
}
unsigned file_offset[TGSI_FILE_COUNT];
unsigned temp_reg;
struct r600_shader_tgsi_instruction *inst_info;
- struct r600_bytecode *bc;
+ struct r600_bytecode *bc;
struct r600_shader *shader;
struct r600_shader_src src[4];
- u32 *literals;
- u32 nliterals;
- u32 max_driver_temp_used;
+ uint32_t *literals;
+ uint32_t nliterals;
+ uint32_t max_driver_temp_used;
/* needed for evergreen interpolation */
boolean input_centroid;
boolean input_linear;
const boolean src_requires_loading = tgsi_tex_src_requires_loading(ctx, 0);
boolean src_loaded = FALSE;
unsigned sampler_src_reg = 1;
- u8 offset_x = 0, offset_y = 0, offset_z = 0;
+ uint8_t offset_x = 0, offset_y = 0, offset_z = 0;
src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
struct r600_pipe_state *rstate;
- u32 color_control = 0, target_mask;
+ uint32_t color_control = 0, target_mask;
if (blend == NULL) {
return NULL;
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 tl, br;
+ uint32_t tl, br;
if (rstate == NULL)
return;
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 shader_mask, tl, br, shader_control;
+ uint32_t shader_mask, tl, br, shader_control;
if (rstate == NULL)
return;
int num_es_stack_entries;
enum radeon_family family;
struct r600_pipe_state *rstate = &rctx->config;
- u32 tmp;
+ uint32_t tmp;
family = rctx->family;
ps_prio = 0;
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
- u32 offset, u32 value,
- u32 range_id, u32 block_id,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
struct r600_resource *bo,
enum radeon_bo_usage usage)
{
}
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- u32 offset, u32 value,
+ uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage)
{
projects / mesa.git / commitdiff