broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.

Apparently the other funcs will have observable differences when early Z
is enabled.

Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.

diff --git a/src/gallium/drivers/vc5/vc5_state.c b/src/gallium/drivers/vc5/vc5_state.c
index 35d5e1df509f26d7cc4819d3276b9cb7327835f8..0d6699ae57b3086a4d4b8d1941c311e8ac5d6e9e 100644 (file)
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -165,8 +165,10 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
                           cso->depth.func == PIPE_FUNC_LEQUAL) &&
                          (!cso->stencil[0].enabled ||
                           (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
+                           cso->stencil[0].func == PIPE_FUNC_ALWAYS &&
                            (!cso->stencil[1].enabled ||
-                            cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
+                            (cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP &&
+                             cso->stencil[1].func == PIPE_FUNC_ALWAYS)))));
         }
 
         const struct pipe_stencil_state *front = &cso->stencil[0];