MIPS: add MT ASE support for micromips32

These instructions are descripted in MD00768.

MIPS® Architecture for Programmers
Volume IV-f: The MIPS® MT Module for
the microMIPS32™ Architecture

Document Number: MD00768
Revision 1.12
July 16, 2013

https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00768-1C-microMIPS32MT-AFP-01.12.pdf

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 47a4fa65e2c2e02b4d2246bf8398ce1459e516d5..71a046c2b69412811ed90d54169055adc90afa7a 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1808,7 +1808,7 @@ static const struct mips_ase mips_ases[] = {
 
   { "mt", ASE_MT, 0,
     OPTION_MT, OPTION_NO_MT,
-     2,  2, -1, -1,
+     2,  2, 2, 2,
     -1 },
 
   { "smartmips", ASE_SMARTMIPS, 0,

diff --git a/gas/testsuite/gas/mips/ase-errors-3.l b/gas/testsuite/gas/mips/ase-errors-3.l
index 77823f220844e0322d6c42d3d5da4967bdfac761..6aa57bf82ad4cd67296df803d5dafad7e68ddc39 100644 (file)
--- a/gas/testsuite/gas/mips/ase-errors-3.l
+++ b/gas/testsuite/gas/mips/ase-errors-3.l
@@ -17,9 +17,6 @@
 .*:34: Warning: the `mips3d' extension requires 64-bit FPRs
 .*:35: Error: unrecognized opcode `addr.ps \$f4,\$f6,\$f8'
 # ----------------------------------------------------------------------------
-.*:39: Warning: the 32-bit microMIPS architecture does not support the `mt' extension
-.*:40: Error: unrecognized opcode `dmt *'
-# ----------------------------------------------------------------------------
 .*:44: Warning: the 32-bit microMIPS architecture does not support the `smartmips' extension
 .*:45: Error: unrecognized opcode `maddp \$4,\$5'
 # ----------------------------------------------------------------------------

diff --git a/gas/testsuite/gas/mips/ase-errors-4.l b/gas/testsuite/gas/mips/ase-errors-4.l
index b473b30e61188948849f000660f0157b862eb385..5bcaeeb8baf14b0242c599d66917cbc71d951064 100644 (file)
--- a/gas/testsuite/gas/mips/ase-errors-4.l
+++ b/gas/testsuite/gas/mips/ase-errors-4.l
@@ -15,9 +15,6 @@
 .*:34: Warning: the 64-bit microMIPS architecture does not support the `mips3d' extension
 .*:35: Error: unrecognized opcode `addr.ps \$f4,\$f6,\$f8'
 # ----------------------------------------------------------------------------
-.*:39: Warning: the 64-bit microMIPS architecture does not support the `mt' extension
-.*:40: Error: unrecognized opcode `dmt *'
-# ----------------------------------------------------------------------------
 .*:44: Warning: the 64-bit microMIPS architecture does not support the `smartmips' extension
 .*:45: Error: unrecognized opcode `maddp \$4,\$5'
 # ----------------------------------------------------------------------------

diff --git a/gas/testsuite/gas/mips/micromips32-mt.d b/gas/testsuite/gas/mips/micromips32-mt.d
new file mode 100644 (file)
index 0000000..7dc56a8
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips32-mt.d
@@ -0,0 +1,635 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32
+#name: MIPS MT ASE for microMIPS32
+#as: -mmt -mmicromips -mips32r2 -32
+#source: mips32-mt.s
+
+# Check MIPS MT ASE for microMIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 0000 057c       dmt
+0+0004 <[^>]*> 03e0 057c       dmt     ra
+0+0008 <[^>]*> 0000 157c       dvpe
+0+000c <[^>]*> 0020 157c       dvpe    at
+0+0010 <[^>]*> 0000 257c       emt
+0+0014 <[^>]*> 0040 257c       emt     v0
+0+0018 <[^>]*> 0000 357c       evpe
+0+001c <[^>]*> 0060 357c       evpe    v1
+0+0020 <[^>]*> 00c5 2027       fork    a0,a1,a2
+0+0024 <[^>]*> 00a0 09bc       yield   a1
+0+0028 <[^>]*> 00e6 09bc       yield   a2,a3
+0+002c <[^>]*> 0107 000e       mftc0   a3,c0_badvaddr
+0+0030 <[^>]*> 0008 000e       mftc0   t0,c0_index
+0+0034 <[^>]*> 0008 001e       mftc0   t0,\$0,1
+0+0038 <[^>]*> 0008 002e       mftc0   t0,\$0,2
+0+003c <[^>]*> 0008 003e       mftc0   t0,\$0,3
+0+0040 <[^>]*> 0008 004e       mftc0   t0,\$0,4
+0+0044 <[^>]*> 0008 005e       mftc0   t0,\$0,5
+0+0048 <[^>]*> 0008 006e       mftc0   t0,\$0,6
+0+004c <[^>]*> 0008 007e       mftc0   t0,\$0,7
+0+0050 <[^>]*> 0028 000e       mftc0   t0,c0_random
+0+0054 <[^>]*> 0028 001e       mftc0   t0,\$1,1
+0+0058 <[^>]*> 0028 002e       mftc0   t0,\$1,2
+0+005c <[^>]*> 0028 003e       mftc0   t0,\$1,3
+0+0060 <[^>]*> 0028 004e       mftc0   t0,\$1,4
+0+0064 <[^>]*> 0028 005e       mftc0   t0,\$1,5
+0+0068 <[^>]*> 0028 006e       mftc0   t0,\$1,6
+0+006c <[^>]*> 0028 007e       mftc0   t0,\$1,7
+0+0070 <[^>]*> 0048 000e       mftc0   t0,c0_entrylo0
+0+0074 <[^>]*> 0048 001e       mftc0   t0,\$2,1
+0+0078 <[^>]*> 0048 002e       mftc0   t0,\$2,2
+0+007c <[^>]*> 0048 003e       mftc0   t0,\$2,3
+0+0080 <[^>]*> 0048 004e       mftc0   t0,\$2,4
+0+0084 <[^>]*> 0048 005e       mftc0   t0,\$2,5
+0+0088 <[^>]*> 0048 006e       mftc0   t0,\$2,6
+0+008c <[^>]*> 0048 007e       mftc0   t0,\$2,7
+0+0090 <[^>]*> 0068 000e       mftc0   t0,c0_entrylo1
+0+0094 <[^>]*> 0068 001e       mftc0   t0,\$3,1
+0+0098 <[^>]*> 0068 002e       mftc0   t0,\$3,2
+0+009c <[^>]*> 0068 003e       mftc0   t0,\$3,3
+0+00a0 <[^>]*> 0068 004e       mftc0   t0,\$3,4
+0+00a4 <[^>]*> 0068 005e       mftc0   t0,\$3,5
+0+00a8 <[^>]*> 0068 006e       mftc0   t0,\$3,6
+0+00ac <[^>]*> 0068 007e       mftc0   t0,\$3,7
+0+00b0 <[^>]*> 0088 000e       mftc0   t0,c0_context
+0+00b4 <[^>]*> 0088 001e       mftc0   t0,\$4,1
+0+00b8 <[^>]*> 0088 002e       mftc0   t0,\$4,2
+0+00bc <[^>]*> 0088 003e       mftc0   t0,\$4,3
+0+00c0 <[^>]*> 0088 004e       mftc0   t0,\$4,4
+0+00c4 <[^>]*> 0088 005e       mftc0   t0,\$4,5
+0+00c8 <[^>]*> 0088 006e       mftc0   t0,\$4,6
+0+00cc <[^>]*> 0088 007e       mftc0   t0,\$4,7
+0+00d0 <[^>]*> 00a8 000e       mftc0   t0,c0_pagemask
+0+00d4 <[^>]*> 00a8 001e       mftc0   t0,\$5,1
+0+00d8 <[^>]*> 00a8 002e       mftc0   t0,\$5,2
+0+00dc <[^>]*> 00a8 003e       mftc0   t0,\$5,3
+0+00e0 <[^>]*> 00a8 004e       mftc0   t0,\$5,4
+0+00e4 <[^>]*> 00a8 005e       mftc0   t0,\$5,5
+0+00e8 <[^>]*> 00a8 006e       mftc0   t0,\$5,6
+0+00ec <[^>]*> 00a8 007e       mftc0   t0,\$5,7
+0+00f0 <[^>]*> 00c8 000e       mftc0   t0,c0_wired
+0+00f4 <[^>]*> 00c8 001e       mftc0   t0,\$6,1
+0+00f8 <[^>]*> 00c8 002e       mftc0   t0,\$6,2
+0+00fc <[^>]*> 00c8 003e       mftc0   t0,\$6,3
+0+0100 <[^>]*> 00c8 004e       mftc0   t0,\$6,4
+0+0104 <[^>]*> 00c8 005e       mftc0   t0,\$6,5
+0+0108 <[^>]*> 00c8 006e       mftc0   t0,\$6,6
+0+010c <[^>]*> 00c8 007e       mftc0   t0,\$6,7
+0+0110 <[^>]*> 00e8 000e       mftc0   t0,\$7
+0+0114 <[^>]*> 00e8 001e       mftc0   t0,\$7,1
+0+0118 <[^>]*> 00e8 002e       mftc0   t0,\$7,2
+0+011c <[^>]*> 00e8 003e       mftc0   t0,\$7,3
+0+0120 <[^>]*> 00e8 004e       mftc0   t0,\$7,4
+0+0124 <[^>]*> 00e8 005e       mftc0   t0,\$7,5
+0+0128 <[^>]*> 00e8 006e       mftc0   t0,\$7,6
+0+012c <[^>]*> 00e8 007e       mftc0   t0,\$7,7
+0+0130 <[^>]*> 0108 000e       mftc0   t0,c0_badvaddr
+0+0134 <[^>]*> 0108 001e       mftc0   t0,\$8,1
+0+0138 <[^>]*> 0108 002e       mftc0   t0,\$8,2
+0+013c <[^>]*> 0108 003e       mftc0   t0,\$8,3
+0+0140 <[^>]*> 0108 004e       mftc0   t0,\$8,4
+0+0144 <[^>]*> 0108 005e       mftc0   t0,\$8,5
+0+0148 <[^>]*> 0108 006e       mftc0   t0,\$8,6
+0+014c <[^>]*> 0108 007e       mftc0   t0,\$8,7
+0+0150 <[^>]*> 0128 000e       mftc0   t0,c0_count
+0+0154 <[^>]*> 0128 001e       mftc0   t0,\$9,1
+0+0158 <[^>]*> 0128 002e       mftc0   t0,\$9,2
+0+015c <[^>]*> 0128 003e       mftc0   t0,\$9,3
+0+0160 <[^>]*> 0128 004e       mftc0   t0,\$9,4
+0+0164 <[^>]*> 0128 005e       mftc0   t0,\$9,5
+0+0168 <[^>]*> 0128 006e       mftc0   t0,\$9,6
+0+016c <[^>]*> 0128 007e       mftc0   t0,\$9,7
+0+0170 <[^>]*> 0148 000e       mftc0   t0,c0_entryhi
+0+0174 <[^>]*> 0148 001e       mftc0   t0,\$10,1
+0+0178 <[^>]*> 0148 002e       mftc0   t0,\$10,2
+0+017c <[^>]*> 0148 003e       mftc0   t0,\$10,3
+0+0180 <[^>]*> 0148 004e       mftc0   t0,\$10,4
+0+0184 <[^>]*> 0148 005e       mftc0   t0,\$10,5
+0+0188 <[^>]*> 0148 006e       mftc0   t0,\$10,6
+0+018c <[^>]*> 0148 007e       mftc0   t0,\$10,7
+0+0190 <[^>]*> 0168 000e       mftc0   t0,c0_compare
+0+0194 <[^>]*> 0168 001e       mftc0   t0,\$11,1
+0+0198 <[^>]*> 0168 002e       mftc0   t0,\$11,2
+0+019c <[^>]*> 0168 003e       mftc0   t0,\$11,3
+0+01a0 <[^>]*> 0168 004e       mftc0   t0,\$11,4
+0+01a4 <[^>]*> 0168 005e       mftc0   t0,\$11,5
+0+01a8 <[^>]*> 0168 006e       mftc0   t0,\$11,6
+0+01ac <[^>]*> 0168 007e       mftc0   t0,\$11,7
+0+01b0 <[^>]*> 0188 000e       mftc0   t0,c0_status
+0+01b4 <[^>]*> 0188 001e       mftc0   t0,\$12,1
+0+01b8 <[^>]*> 0188 002e       mftc0   t0,\$12,2
+0+01bc <[^>]*> 0188 003e       mftc0   t0,\$12,3
+0+01c0 <[^>]*> 0188 004e       mftc0   t0,\$12,4
+0+01c4 <[^>]*> 0188 005e       mftc0   t0,\$12,5
+0+01c8 <[^>]*> 0188 006e       mftc0   t0,\$12,6
+0+01cc <[^>]*> 0188 007e       mftc0   t0,\$12,7
+0+01d0 <[^>]*> 01a8 000e       mftc0   t0,c0_cause
+0+01d4 <[^>]*> 01a8 001e       mftc0   t0,\$13,1
+0+01d8 <[^>]*> 01a8 002e       mftc0   t0,\$13,2
+0+01dc <[^>]*> 01a8 003e       mftc0   t0,\$13,3
+0+01e0 <[^>]*> 01a8 004e       mftc0   t0,\$13,4
+0+01e4 <[^>]*> 01a8 005e       mftc0   t0,\$13,5
+0+01e8 <[^>]*> 01a8 006e       mftc0   t0,\$13,6
+0+01ec <[^>]*> 01a8 007e       mftc0   t0,\$13,7
+0+01f0 <[^>]*> 01c8 000e       mftc0   t0,c0_epc
+0+01f4 <[^>]*> 01c8 001e       mftc0   t0,\$14,1
+0+01f8 <[^>]*> 01c8 002e       mftc0   t0,\$14,2
+0+01fc <[^>]*> 01c8 003e       mftc0   t0,\$14,3
+0+0200 <[^>]*> 01c8 004e       mftc0   t0,\$14,4
+0+0204 <[^>]*> 01c8 005e       mftc0   t0,\$14,5
+0+0208 <[^>]*> 01c8 006e       mftc0   t0,\$14,6
+0+020c <[^>]*> 01c8 007e       mftc0   t0,\$14,7
+0+0210 <[^>]*> 01e8 000e       mftc0   t0,c0_prid
+0+0214 <[^>]*> 01e8 001e       mftc0   t0,\$15,1
+0+0218 <[^>]*> 01e8 002e       mftc0   t0,\$15,2
+0+021c <[^>]*> 01e8 003e       mftc0   t0,\$15,3
+0+0220 <[^>]*> 01e8 004e       mftc0   t0,\$15,4
+0+0224 <[^>]*> 01e8 005e       mftc0   t0,\$15,5
+0+0228 <[^>]*> 01e8 006e       mftc0   t0,\$15,6
+0+022c <[^>]*> 01e8 007e       mftc0   t0,\$15,7
+0+0230 <[^>]*> 0208 000e       mftc0   t0,c0_config
+0+0234 <[^>]*> 0208 001e       mftc0   t0,c0_config1
+0+0238 <[^>]*> 0208 002e       mftc0   t0,c0_config2
+0+023c <[^>]*> 0208 003e       mftc0   t0,c0_config3
+0+0240 <[^>]*> 0208 004e       mftc0   t0,\$16,4
+0+0244 <[^>]*> 0208 005e       mftc0   t0,\$16,5
+0+0248 <[^>]*> 0208 006e       mftc0   t0,\$16,6
+0+024c <[^>]*> 0208 007e       mftc0   t0,\$16,7
+0+0250 <[^>]*> 0228 000e       mftc0   t0,c0_lladdr
+0+0254 <[^>]*> 0228 001e       mftc0   t0,\$17,1
+0+0258 <[^>]*> 0228 002e       mftc0   t0,\$17,2
+0+025c <[^>]*> 0228 003e       mftc0   t0,\$17,3
+0+0260 <[^>]*> 0228 004e       mftc0   t0,\$17,4
+0+0264 <[^>]*> 0228 005e       mftc0   t0,\$17,5
+0+0268 <[^>]*> 0228 006e       mftc0   t0,\$17,6
+0+026c <[^>]*> 0228 007e       mftc0   t0,\$17,7
+0+0270 <[^>]*> 0248 000e       mftc0   t0,c0_watchlo
+0+0274 <[^>]*> 0248 001e       mftc0   t0,c0_watchlo,1
+0+0278 <[^>]*> 0248 002e       mftc0   t0,c0_watchlo,2
+0+027c <[^>]*> 0248 003e       mftc0   t0,c0_watchlo,3
+0+0280 <[^>]*> 0248 004e       mftc0   t0,c0_watchlo,4
+0+0284 <[^>]*> 0248 005e       mftc0   t0,c0_watchlo,5
+0+0288 <[^>]*> 0248 006e       mftc0   t0,c0_watchlo,6
+0+028c <[^>]*> 0248 007e       mftc0   t0,c0_watchlo,7
+0+0290 <[^>]*> 0268 000e       mftc0   t0,c0_watchhi
+0+0294 <[^>]*> 0268 001e       mftc0   t0,c0_watchhi,1
+0+0298 <[^>]*> 0268 002e       mftc0   t0,c0_watchhi,2
+0+029c <[^>]*> 0268 003e       mftc0   t0,c0_watchhi,3
+0+02a0 <[^>]*> 0268 004e       mftc0   t0,c0_watchhi,4
+0+02a4 <[^>]*> 0268 005e       mftc0   t0,c0_watchhi,5
+0+02a8 <[^>]*> 0268 006e       mftc0   t0,c0_watchhi,6
+0+02ac <[^>]*> 0268 007e       mftc0   t0,c0_watchhi,7
+0+02b0 <[^>]*> 0288 000e       mftc0   t0,c0_xcontext
+0+02b4 <[^>]*> 0288 001e       mftc0   t0,\$20,1
+0+02b8 <[^>]*> 0288 002e       mftc0   t0,\$20,2
+0+02bc <[^>]*> 0288 003e       mftc0   t0,\$20,3
+0+02c0 <[^>]*> 0288 004e       mftc0   t0,\$20,4
+0+02c4 <[^>]*> 0288 005e       mftc0   t0,\$20,5
+0+02c8 <[^>]*> 0288 006e       mftc0   t0,\$20,6
+0+02cc <[^>]*> 0288 007e       mftc0   t0,\$20,7
+0+02d0 <[^>]*> 02a8 000e       mftc0   t0,\$21
+0+02d4 <[^>]*> 02a8 001e       mftc0   t0,\$21,1
+0+02d8 <[^>]*> 02a8 002e       mftc0   t0,\$21,2
+0+02dc <[^>]*> 02a8 003e       mftc0   t0,\$21,3
+0+02e0 <[^>]*> 02a8 004e       mftc0   t0,\$21,4
+0+02e4 <[^>]*> 02a8 005e       mftc0   t0,\$21,5
+0+02e8 <[^>]*> 02a8 006e       mftc0   t0,\$21,6
+0+02ec <[^>]*> 02a8 007e       mftc0   t0,\$21,7
+0+02f0 <[^>]*> 02c8 000e       mftc0   t0,\$22
+0+02f4 <[^>]*> 02c8 001e       mftc0   t0,\$22,1
+0+02f8 <[^>]*> 02c8 002e       mftc0   t0,\$22,2
+0+02fc <[^>]*> 02c8 003e       mftc0   t0,\$22,3
+0+0300 <[^>]*> 02c8 004e       mftc0   t0,\$22,4
+0+0304 <[^>]*> 02c8 005e       mftc0   t0,\$22,5
+0+0308 <[^>]*> 02c8 006e       mftc0   t0,\$22,6
+0+030c <[^>]*> 02c8 007e       mftc0   t0,\$22,7
+0+0310 <[^>]*> 02e8 000e       mftc0   t0,c0_debug
+0+0314 <[^>]*> 02e8 001e       mftc0   t0,\$23,1
+0+0318 <[^>]*> 02e8 002e       mftc0   t0,\$23,2
+0+031c <[^>]*> 02e8 003e       mftc0   t0,\$23,3
+0+0320 <[^>]*> 02e8 004e       mftc0   t0,\$23,4
+0+0324 <[^>]*> 02e8 005e       mftc0   t0,\$23,5
+0+0328 <[^>]*> 02e8 006e       mftc0   t0,\$23,6
+0+032c <[^>]*> 02e8 007e       mftc0   t0,\$23,7
+0+0330 <[^>]*> 0308 000e       mftc0   t0,c0_depc
+0+0334 <[^>]*> 0308 001e       mftc0   t0,\$24,1
+0+0338 <[^>]*> 0308 002e       mftc0   t0,\$24,2
+0+033c <[^>]*> 0308 003e       mftc0   t0,\$24,3
+0+0340 <[^>]*> 0308 004e       mftc0   t0,\$24,4
+0+0344 <[^>]*> 0308 005e       mftc0   t0,\$24,5
+0+0348 <[^>]*> 0308 006e       mftc0   t0,\$24,6
+0+034c <[^>]*> 0308 007e       mftc0   t0,\$24,7
+0+0350 <[^>]*> 0328 000e       mftc0   t0,c0_perfcnt
+0+0354 <[^>]*> 0328 001e       mftc0   t0,c0_perfcnt,1
+0+0358 <[^>]*> 0328 002e       mftc0   t0,c0_perfcnt,2
+0+035c <[^>]*> 0328 003e       mftc0   t0,c0_perfcnt,3
+0+0360 <[^>]*> 0328 004e       mftc0   t0,c0_perfcnt,4
+0+0364 <[^>]*> 0328 005e       mftc0   t0,c0_perfcnt,5
+0+0368 <[^>]*> 0328 006e       mftc0   t0,c0_perfcnt,6
+0+036c <[^>]*> 0328 007e       mftc0   t0,c0_perfcnt,7
+0+0370 <[^>]*> 0348 000e       mftc0   t0,c0_errctl
+0+0374 <[^>]*> 0348 001e       mftc0   t0,\$26,1
+0+0378 <[^>]*> 0348 002e       mftc0   t0,\$26,2
+0+037c <[^>]*> 0348 003e       mftc0   t0,\$26,3
+0+0380 <[^>]*> 0348 004e       mftc0   t0,\$26,4
+0+0384 <[^>]*> 0348 005e       mftc0   t0,\$26,5
+0+0388 <[^>]*> 0348 006e       mftc0   t0,\$26,6
+0+038c <[^>]*> 0348 007e       mftc0   t0,\$26,7
+0+0390 <[^>]*> 0368 000e       mftc0   t0,c0_cacheerr
+0+0394 <[^>]*> 0368 001e       mftc0   t0,c0_cacheerr,1
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+0+07c8 <[^>]*> 037a 0046       mttc0   k1,\$26,4
+0+07cc <[^>]*> 037a 0056       mttc0   k1,\$26,5
+0+07d0 <[^>]*> 037a 0066       mttc0   k1,\$26,6
+0+07d4 <[^>]*> 037a 0076       mttc0   k1,\$26,7
+0+07d8 <[^>]*> 037b 0006       mttc0   k1,c0_cacheerr
+0+07dc <[^>]*> 037b 0016       mttc0   k1,c0_cacheerr,1
+0+07e0 <[^>]*> 037b 0026       mttc0   k1,c0_cacheerr,2
+0+07e4 <[^>]*> 037b 0036       mttc0   k1,c0_cacheerr,3
+0+07e8 <[^>]*> 037b 0046       mttc0   k1,\$27,4
+0+07ec <[^>]*> 037b 0056       mttc0   k1,\$27,5
+0+07f0 <[^>]*> 037b 0066       mttc0   k1,\$27,6
+0+07f4 <[^>]*> 037b 0076       mttc0   k1,\$27,7
+0+07f8 <[^>]*> 037c 0006       mttc0   k1,c0_taglo
+0+07fc <[^>]*> 037c 0016       mttc0   k1,c0_datalo
+0+0800 <[^>]*> 037c 0026       mttc0   k1,\$28,2
+0+0804 <[^>]*> 037c 0036       mttc0   k1,\$28,3
+0+0808 <[^>]*> 037c 0046       mttc0   k1,\$28,4
+0+080c <[^>]*> 037c 0056       mttc0   k1,\$28,5
+0+0810 <[^>]*> 037c 0066       mttc0   k1,\$28,6
+0+0814 <[^>]*> 037c 0076       mttc0   k1,\$28,7
+0+0818 <[^>]*> 037d 0006       mttc0   k1,c0_taghi
+0+081c <[^>]*> 037d 0016       mttc0   k1,c0_datahi
+0+0820 <[^>]*> 037d 0026       mttc0   k1,\$29,2
+0+0824 <[^>]*> 037d 0036       mttc0   k1,\$29,3
+0+0828 <[^>]*> 037d 0046       mttc0   k1,\$29,4
+0+082c <[^>]*> 037d 0056       mttc0   k1,\$29,5
+0+0830 <[^>]*> 037d 0066       mttc0   k1,\$29,6
+0+0834 <[^>]*> 037d 0076       mttc0   k1,\$29,7
+0+0838 <[^>]*> 037e 0006       mttc0   k1,c0_errorepc
+0+083c <[^>]*> 037e 0016       mttc0   k1,\$30,1
+0+0840 <[^>]*> 037e 0026       mttc0   k1,\$30,2
+0+0844 <[^>]*> 037e 0036       mttc0   k1,\$30,3
+0+0848 <[^>]*> 037e 0046       mttc0   k1,\$30,4
+0+084c <[^>]*> 037e 0056       mttc0   k1,\$30,5
+0+0850 <[^>]*> 037e 0066       mttc0   k1,\$30,6
+0+0854 <[^>]*> 037e 0076       mttc0   k1,\$30,7
+0+0858 <[^>]*> 037f 0006       mttc0   k1,c0_desave
+0+085c <[^>]*> 037f 0016       mttc0   k1,\$31,1
+0+0860 <[^>]*> 037f 0026       mttc0   k1,\$31,2
+0+0864 <[^>]*> 037f 0036       mttc0   k1,\$31,3
+0+0868 <[^>]*> 037f 0046       mttc0   k1,\$31,4
+0+086c <[^>]*> 037f 0056       mttc0   k1,\$31,5
+0+0870 <[^>]*> 037f 0066       mttc0   k1,\$31,6
+0+0874 <[^>]*> 037f 0076       mttc0   k1,\$31,7
+0+0878 <[^>]*> 039d 0406       mttgpr  gp,sp
+0+087c <[^>]*> 03a0 0416       mttlo   sp
+0+0880 <[^>]*> 03cc 0416       mttlo   s8,\$ac3
+0+0884 <[^>]*> 03e1 0416       mtthi   ra
+0+0888 <[^>]*> 0001 0416       mtthi   zero
+0+088c <[^>]*> 0022 0416       mttacx  at
+0+0890 <[^>]*> 0046 0416       mttacx  v0,\$ac1
+0+0894 <[^>]*> 0070 0416       mttdsp  v1
+0+0898 <[^>]*> 0085 0426       mttc1   a0,\$f5
+0+089c <[^>]*> 00a6 0426       mttc1   a1,\$f6
+0+08a0 <[^>]*> 00c8 0626       mtthc1  a2,\$f8
+0+08a4 <[^>]*> 00ea 0626       mtthc1  a3,\$f10
+0+08a8 <[^>]*> 0109 0436       cttc1   t0,\$9
+0+08ac <[^>]*> 012a 0436       cttc1   t1,\$10
+0+08b0 <[^>]*> 014b 0446       mttc2   t2,\$11
+0+08b4 <[^>]*> 016c 0646       mtthc2  t3,\$12
+0+08b8 <[^>]*> 018d 0456       cttc2   t4,\$13
+0+08bc <[^>]*> 01cd 000e       mftc0   t5,c0_epc
+0+08c0 <[^>]*> 01cd 001e       mftc0   t5,\$14,1
+0+08c4 <[^>]*> 01cd 002e       mftc0   t5,\$14,2
+0+08c8 <[^>]*> 01cd 003e       mftc0   t5,\$14,3
+0+08cc <[^>]*> 01cd 004e       mftc0   t5,\$14,4
+0+08d0 <[^>]*> 01cd 005e       mftc0   t5,\$14,5
+0+08d4 <[^>]*> 01cd 006e       mftc0   t5,\$14,6
+0+08d8 <[^>]*> 01cd 007e       mftc0   t5,\$14,7
+0+08dc <[^>]*> 01cd 020e       mftr    t5,t6,0,0,1
+0+08e0 <[^>]*> 01cd 021e       mftr    t5,t6,0,1,1
+0+08e4 <[^>]*> 01cd 022e       mftr    t5,t6,0,2,1
+0+08e8 <[^>]*> 01cd 023e       mftr    t5,t6,0,3,1
+0+08ec <[^>]*> 01cd 024e       mftr    t5,t6,0,4,1
+0+08f0 <[^>]*> 01cd 025e       mftr    t5,t6,0,5,1
+0+08f4 <[^>]*> 01cd 026e       mftr    t5,t6,0,6,1
+0+08f8 <[^>]*> 01cd 027e       mftr    t5,t6,0,7,1
+0+08fc <[^>]*> 01cd 040e       mftgpr  t5,t6
+0+0900 <[^>]*> 01cd 041e       mftacx  t5,\$ac3
+0+0904 <[^>]*> 01cd 042e       mftc1   t5,\$f14
+0+0908 <[^>]*> 01cd 043e       cftc1   t5,\$14
+0+090c <[^>]*> 01cd 044e       mftc2   t5,\$14
+0+0910 <[^>]*> 01cd 045e       cftc2   t5,\$14
+0+0914 <[^>]*> 01cd 046e       mftr    t5,t6,1,6,0
+0+0918 <[^>]*> 01cd 047e       mftr    t5,t6,1,7,0
+0+091c <[^>]*> 01cd 060e       mftr    t5,t6,1,0,1
+0+0920 <[^>]*> 01cd 061e       mftr    t5,t6,1,1,1
+0+0924 <[^>]*> 01cd 062e       mfthc1  t5,\$f14
+0+0928 <[^>]*> 01cd 063e       mftr    t5,t6,1,3,1
+0+092c <[^>]*> 01cd 064e       mfthc2  t5,\$14
+0+0930 <[^>]*> 01cd 065e       mftr    t5,t6,1,5,1
+0+0934 <[^>]*> 01cd 066e       mftr    t5,t6,1,6,1
+0+0938 <[^>]*> 01cd 067e       mftr    t5,t6,1,7,1
+0+093c <[^>]*> 01ae 0006       mttc0   t5,c0_epc
+0+0940 <[^>]*> 01ae 0016       mttc0   t5,\$14,1
+0+0944 <[^>]*> 01ae 0026       mttc0   t5,\$14,2
+0+0948 <[^>]*> 01ae 0036       mttc0   t5,\$14,3
+0+094c <[^>]*> 01ae 0046       mttc0   t5,\$14,4
+0+0950 <[^>]*> 01ae 0056       mttc0   t5,\$14,5
+0+0954 <[^>]*> 01ae 0066       mttc0   t5,\$14,6
+0+0958 <[^>]*> 01ae 0076       mttc0   t5,\$14,7
+0+095c <[^>]*> 01ae 0206       mttr    t5,t6,0,0,1
+0+0960 <[^>]*> 01ae 0216       mttr    t5,t6,0,1,1
+0+0964 <[^>]*> 01ae 0226       mttr    t5,t6,0,2,1
+0+0968 <[^>]*> 01ae 0236       mttr    t5,t6,0,3,1
+0+096c <[^>]*> 01ae 0246       mttr    t5,t6,0,4,1
+0+0970 <[^>]*> 01ae 0256       mttr    t5,t6,0,5,1
+0+0974 <[^>]*> 01ae 0266       mttr    t5,t6,0,6,1
+0+0978 <[^>]*> 01ae 0276       mttr    t5,t6,0,7,1
+0+097c <[^>]*> 01ae 0406       mttgpr  t5,t6
+0+0980 <[^>]*> 01ae 0416       mttacx  t5,\$ac3
+0+0984 <[^>]*> 01ae 0426       mttc1   t5,\$f14
+0+0988 <[^>]*> 01ae 0436       cttc1   t5,\$14
+0+098c <[^>]*> 01ae 0446       mttc2   t5,\$14
+0+0990 <[^>]*> 01ae 0456       cttc2   t5,\$14
+0+0994 <[^>]*> 01ae 0466       mttr    t5,t6,1,6,0
+0+0998 <[^>]*> 01ae 0476       mttr    t5,t6,1,7,0
+0+099c <[^>]*> 01ae 0606       mttr    t5,t6,1,0,1
+0+09a0 <[^>]*> 01ae 0616       mttr    t5,t6,1,1,1
+0+09a4 <[^>]*> 01ae 0626       mtthc1  t5,\$f14
+0+09a8 <[^>]*> 01ae 0636       mttr    t5,t6,1,3,1
+0+09ac <[^>]*> 01ae 0646       mtthc2  t5,\$14
+0+09b0 <[^>]*> 01ae 0656       mttr    t5,t6,1,5,1
+0+09b4 <[^>]*> 01ae 0666       mttr    t5,t6,1,6,1
+0+09b8 <[^>]*> 01ae 0676       mttr    t5,t6,1,7,1
+0+09bc <[^>]*> 0000 2800       pause
+       \.\.\.

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index b21f529e466ac3875bed29568c550c0e59c92c9a..0ea673906a77ee52b0b94382b65bee179bf87356 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1483,6 +1483,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "mips32-dspr3"        [mips_arch_list_matching mips32r6]
     run_dump_test "mips64-dsp"
     run_dump_test "mips32-mt"
+    run_dump_test "micromips32-mt"
 
     run_dump_test_arches "save" [lsort -dictionary -unique [concat \
                                [mips_arch_list_matching mips16e-32] \

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 94812a68c82d17dabcf3ad9f191ac41a4641e2c0..5a6460d9b8b12d206d263e1445c976841928d50c 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -148,6 +148,10 @@ decode_micromips_operand (const char *p)
     case '~': SINT (12, 0);
     case '@': SINT (10, 16);
     case '^': HINT (5, 11);
+    case '*': REG (2, 23, ACC);
+    case '!': UINT (1, 10);
+    case '$': UINT (1, 9);
+    case '&': REG (2, 18, ACC);
 
     case '0': SINT (6, 16);
     case '1': HINT (5, 16);
@@ -165,6 +169,7 @@ decode_micromips_operand (const char *p)
     case 'G': REG (5, 16, COPRO);
     case 'K': REG (5, 16, HW);
     case 'H': UINT (3, 11);
+    case 'O': UINT (3, 4);
     case 'M': REG (3, 13, CCC);
     case 'N': REG (3, 18, CCC);
     case 'R': REG (5, 6, FP);
@@ -264,6 +269,9 @@ decode_micromips_operand (const char *p)
 #define D32    ASE_DSP
 #define D33    ASE_DSPR2
 
+/* microMIPS MT ASE support.  */
+#define MT32   ASE_MT
+
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC     ASE_MCU
 
@@ -552,11 +560,19 @@ const struct mips_opcode micromips_opcodes[] =
 {"cfc1",               "t,g",          0x5400103b, 0xfc00ffff, WR_1|RD_C1,             0,              I1,             0,      0 },
 {"cfc1",               "t,S",          0x5400103b, 0xfc00ffff, WR_1|RD_C1,             0,              I1,             0,      0 },
 {"cfc2",               "t,g",          0x0000cd3c, 0xfc00ffff, WR_1|RD_C2,             0,              I1,             0,      0 },
+{"cftc1",              "s,E",          0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc1",              "s,T",          0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc2",              "s,E",          0x0000045e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc2",              "s,E,h",        0x0000045e, 0xfc0007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
 {"clo",                        "t,s",          0x00004b3c, 0xfc00ffff, WR_1|RD_2,              0,              I1,             0,      0 },
 {"clz",                        "t,s",          0x00005b3c, 0xfc00ffff, WR_1|RD_2,              0,              I1,             0,      0 },
 {"cop2",               "C",            0x00000002, 0xfc000007, CP,                     0,              I1,             0,      0 },
 {"ctc1",               "t,g",          0x5400183b, 0xfc00ffff, RD_1|WR_CC,             0,              I1,             0,      0 },
 {"ctc1",               "t,S",          0x5400183b, 0xfc00ffff, RD_1|WR_CC,             0,              I1,             0,      0 },
+{"cttc1",              "t,g",          0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
+{"cttc1",              "t,S",          0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
+{"cttc2",              "t,G",          0x00000456, 0xfc00ffff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
+{"cttc2",              "t,G,h",        0x00000456, 0xfc0007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
 {"ctc2",               "t,g",          0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I1,             0,      0 },
 {"cvt.d.l",            "T,S",          0x5400537b, 0xfc00ffff, WR_1|RD_2|FP_D,         0,              I1,             0,      0 },
 {"cvt.d.s",            "T,S",          0x5400137b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      0 },
@@ -640,6 +656,8 @@ const struct mips_opcode micromips_opcodes[] =
 /*{"dmfc2",            "t,G,H",        0x58000283, 0xfc001fff, WR_1|RD_C2,             0,              I3,             0,      0 },*/
 {"dmtc2",              "t,G",          0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC,       0,              I3,             0,      0 },
 /*{"dmtc2",            "t,G,H",        0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC,       0,              I3,             0,      0 },*/
+{"dmt",                        "",             0x0000057c, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
+{"dmt",                        "t",            0x0000057c, 0xfc1fffff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"dmul",               "d,v,t",        0,    (int) M_DMUL,     INSN_MACRO,             0,              I3,             0,      0 },
 {"dmul",               "d,v,I",        0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3,             0,      0 },
 {"dmulo",              "d,v,t",        0,    (int) M_DMULO,    INSN_MACRO,             0,              I3,             0,      0 },
@@ -648,6 +666,8 @@ const struct mips_opcode micromips_opcodes[] =
 {"dmulou",             "d,v,I",        0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3,             0,      0 },
 {"dmult",              "s,t",          0x58008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              I3,             0,      0 },
 {"dmultu",             "s,t",          0x58009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              I3,             0,      0 },
+{"dvpe",               "",             0x0000157c, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
+{"dvpe",               "t",            0x0000157c, 0xfc1fffff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"dneg",               "d,w",          0x58000190, 0xfc1f07ff, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsub 0 */
 {"dnegu",              "d,w",          0x580001d0, 0xfc1f07ff, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsubu 0 */
 {"drem",               "z,s,t",        0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      0 },
@@ -692,13 +712,18 @@ const struct mips_opcode micromips_opcodes[] =
 {"dsubu",              "d,v,I",        0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"ei",                 "",             0x0000577c, 0xffffffff, WR_C0,                  0,              I1,             0,      0 },
 {"ei",                 "s",            0x0000577c, 0xffe0ffff, WR_1|WR_C0,             0,              I1,             0,      0 },
+{"emt",                        "",             0x0000257c, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
+{"emt",                        "t",            0x0000257c, 0xfc1fffff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"eret",               "",             0x0000f37c, 0xffffffff, NODS,                   0,              I1,             0,      0 },
 {"eretnc",             "",             0x0001f37c, 0xffffffff, NODS,                   0,              I36,            0,      0 },
+{"evpe",               "",             0x0000357c, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
+{"evpe",               "t",            0x0000357c, 0xfc1fffff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"ext",                        "t,r,+A,+C",    0x0000002c, 0xfc00003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"floor.l.d",          "T,V",          0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D,         0,              I1,             0,      0 },
 {"floor.l.s",          "T,V",          0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      0 },
 {"floor.w.d",          "T,V",          0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      0 },
 {"floor.w.s",          "T,V",          0x54000b3b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
+{"fork",               "d,s,t",        0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP,    0,              0,              MT32,   0 },
 {"hypcall",            "",             0x0000c37c, 0xffffffff, TRAP,                   0,              0,              IVIRT,  0 },
 {"hypcall",            "+J",           0x0000c37c, 0xfc00ffff, TRAP,                   0,              0,              IVIRT,  0 },
 {"ins",                        "t,r,+A,+B",    0x0000000c, 0xfc00003f, WR_1|RD_2,              0,              I1,             0,      0 },
@@ -853,6 +878,25 @@ const struct mips_opcode micromips_opcodes[] =
 {"mflo",               "mj",               0x4640,     0xffe0, WR_1|RD_LO,             0,              I1,             0,      0 },
 {"mflo",               "s",            0x00001d7c, 0xffe0ffff, WR_1|RD_LO,             0,              I1,             0,      0 },
 {"mflo",               "s,7",          0x0000107c, 0xffe03fff, WR_1|RD_LO,             0,              0,              D32,    0 },
+{"mftacx",             "s",            0x0040041e, 0xffe0ffff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
+{"mftacx",             "s,*",          0x0040041e, 0xfe60ffff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
+{"mftc0",              "s,E",          0x0000000e, 0xfc00ffff, WR_1|RD_C0|TRAP|LC,     0,              0,              MT32,   0 },
+{"mftc0",              "s,E,O",        0x0000000e, 0xfc00ff8f, WR_1|RD_C0|TRAP|LC,     0,              0,              MT32,   0 },
+{"mftc1",              "s,T",          0x0000042e, 0xfc00ffff, WR_1|RD_2|TRAP|LC|FP_S, 0,              0,              MT32,   0 },
+{"mftc1",              "s,E",          0x0000042e, 0xfc00ffff, WR_1|RD_2|TRAP|LC|FP_S, 0,              0,              MT32,   0 },
+{"mftc2",              "s,E",          0x0000044e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
+{"mftc2",              "s,E,h",        0x0000044e, 0xfc0007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
+{"mfthc1",             "s,T",          0x0000062e, 0xfc00ffff, WR_1|RD_2|TRAP|LC|FP_D, 0,              0,              MT32,   0 },
+{"mfthc1",             "s,E",          0x0000062e, 0xfc00ffff, WR_1|RD_2|TRAP|LC|FP_D, 0,              0,              MT32,   0 },
+{"mfthc2",             "s,E",          0x0000064e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
+{"mfthc2",             "s,E,h",        0x0000064e, 0xfc0007ff, WR_1|RD_C2|TRAP|LC,     0,              0,              MT32,   0 },
+{"mftdsp",             "s",            0x0200041e, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
+{"mftgpr",             "s,t",          0x0000040e, 0xfc00ffff, WR_1|RD_2|TRAP,         0,              0,              MT32,   0 },
+{"mfthi",              "s",            0x0020041e, 0xffe0ffff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
+{"mfthi",              "s,*",          0x0020041e, 0xfe60ffff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
+{"mftlo",              "s",            0x0000041e, 0xffe0ffff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
+{"mftlo",              "s,*",          0x0000041e, 0xfe60ffff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
+{"mftr",               "s,t,!,O,$",    0x0000000e, 0xfc00f98f, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"mov.d",              "T,S",          0x5400207b, 0xfc00ffff, WR_1|RD_2|FP_D,         0,              I1,             0,      0 },
 {"mov.s",              "T,S",          0x5400007b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
 {"mov.ps",             "T,S",          0x5400407b, 0xfc00ffff, WR_1|RD_2|FP_D,         0,              I1,             0,      0 },
@@ -901,6 +945,25 @@ const struct mips_opcode micromips_opcodes[] =
 {"mthi",               "s,7",          0x0000207c, 0xffe03fff, RD_1|WR_HI,             0,              0,              D32,    0 },
 {"mtlo",               "s",            0x00003d7c, 0xffe0ffff, RD_1|WR_LO,             0,              I1,             0,      0 },
 {"mtlo",               "s,7",          0x0000307c, 0xffe03fff, RD_1|WR_LO,             0,              0,              D32,    0 },
+{"mttacx",             "t",            0x00020416, 0xfc1fffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
+{"mttacx",             "t,&",          0x00020416, 0xfc13ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
+{"mttc0",              "t,G",          0x00000006, 0xfc00ffff, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc0",              "t,G,O",        0x00000006, 0xfc00ff8f, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc1",              "t,S",          0x00000426, 0xfc00ffff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
+{"mttc1",              "t,G",          0x00000426, 0xfc00ffff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
+{"mttc2",              "t,G",          0x00000446, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc2",              "t,G,h",        0x00000446, 0xfc0007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mtthc1",             "t,S",          0x00000626, 0xfc00ffff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
+{"mtthc1",             "t,G",          0x00000626, 0xfc00ffff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
+{"mtthc2",             "t,G",          0x00000646, 0xfc00ffff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mtthc2",             "t,G,h",        0x00000646, 0xfc0007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttdsp",             "t",            0x00100416, 0xfc1fffff, RD_1|TRAP,              0,              0,              MT32,   0 },
+{"mttgpr",             "t,s",          0x00000406, 0xfc00ffff, RD_1|WR_2|TRAP,         0,              0,              MT32,   0 },
+{"mtthi",              "t",            0x00010416, 0xfc1fffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
+{"mtthi",              "t,&",          0x00010416, 0xfc13ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
+{"mttlo",              "t",            0x00000416, 0xfc1fffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
+{"mttlo",              "t,&",          0x00000416, 0xfc13ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
+{"mttr",               "t,s,!,O,$",    0x00000006, 0xfc00f98f, RD_1|TRAP,              0,              0,              MT32,   0 },
 {"mul",                        "d,v,t",        0x00000210, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              I1,             0,      0 },
 {"mul",                        "d,v,I",        0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"mul.d",              "D,V,T",        0x540001b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      0 },
@@ -1151,6 +1214,8 @@ const struct mips_opcode micromips_opcodes[] =
 {"xor",                        "d,v,t",        0x00000310, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"xor",                        "t,r,I",        0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"xori",               "t,r,i",        0x70000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
+{"yield",              "t",            0x000009bc, 0xfc1fffff, RD_1|NODS,              0,              0,              MT32,   0 },
+{"yield",              "s,t",          0x000009bc, 0xfc00ffff, WR_1|RD_2|NODS,         0,              0,              MT32,   0 },
 /* microMIPS Enhanced VA Scheme */
 {"lbue",               "t,+j(b)",      0x60006000, 0xfc00fe00, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lbue",               "t,A(b)",       0,    (int) M_LBUE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 859d4e3806fa506468d5074645ef777a4d5b4550..de7d4058300f8e3260453aa4c04b623837c72724 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1921,7 +1921,7 @@ print_insn_args (struct disassemble_info *info,
            }
          else if (operand->type == OP_REG
                   && s[1] == ','
-                  && s[2] == 'H'
+                  && (s[2] == 'H' || s[2] == 'O')
                   && opcode->name[strlen (opcode->name) - 1] == '0')
            {
              /* Coprocessor register 0 with sel field.  */