xilinx/viviado: Allow yosys for synthesis.

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 9e90e3426258d35d4f03fef7559b866aecadbe55..1006ab4098605ce92570b0910dc77fe6bd2ed0b0 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -1,5 +1,6 @@
 import os
 import sys
+import subprocess
 try:
     import colorama
     colorama.init()  # install escape sequence translation on Windows
@@ -223,3 +224,23 @@ xilinx_ku_special_overrides = {
     DDROutput:              XilinxDDROutputKU,
     DDRInput:               XilinxDDRInputKU
 }
+
+
+def _run_yosys(device, sources, vincpaths, build_name):
+    ys_contents = ""
+    incflags = ""
+    for path in vincpaths:
+        incflags += " -I" + path
+    for filename, language, library in sources:
+        ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
+
+    ys_contents += """\
+# hierarchy -top top
+# proc; memory; opt; fsm; opt
+synth_xilinx -top top -edif {build_name}.edif""".format(build_name=build_name)
+
+    ys_name = build_name + ".ys"
+    tools.write_to_file(ys_name, ys_contents)
+    r = subprocess.call(["yosys", ys_name])
+    if r != 0:
+        raise OSError("Subprocess failed")

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 709f746d78bde5e54ef8d55393600d8490e87187..f0c2aecf0d5c2d7850ff9229c5736c681222f883 100644 (file)
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -106,14 +106,17 @@ class XilinxVivadoToolchain:
         self.clocks = dict()
         self.false_paths = set()
 
-    def _build_batch(self, platform, sources, edifs, ips, build_name):
+    def _build_batch(self, platform, sources, edifs, ips, build_name, synth_mode="vivado"):
         tcl = []
         tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device))
-        for filename, language, library in sources:
-            filename_tcl = "{" + filename + "}"
-            tcl.append("add_files " + filename_tcl)
-            tcl.append("set_property library {} [get_files {}]"
-                       .format(library, filename_tcl))
+        if synth_mode == "vivado":
+            # "-include_dirs {}" crashes Vivado 2016.4
+            for filename, language, library in sources:
+                filename_tcl = "{" + filename + "}"
+                tcl.append("add_files " + filename_tcl)
+                tcl.append("set_property library {} [get_files {}]"
+                           .format(library, filename_tcl))
+
         for filename in edifs:
             filename_tcl = "{" + filename + "}"
             tcl.append("read_edif " + filename_tcl)
@@ -129,11 +132,18 @@ class XilinxVivadoToolchain:
 
         tcl.append("read_xdc {}.xdc".format(build_name))
         tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
-        # "-include_dirs {}" crashes Vivado 2016.4
-        if platform.verilog_include_paths:
-            tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
+
+        if synth_mode == "vivado":
+            if platform.verilog_include_paths:
+                tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
+            else:
+                tcl.append("synth_design -top {} -part {}".format(build_name, platform.device))
+        elif synth_mode == "yosys":
+            tcl.append("read_edif {}.edif".format(build_name))
+            tcl.append("link_design -top {} -part {}".format(build_name, platform.device))
         else:
-            tcl.append("synth_design -top {} -part {}".format(build_name, platform.device))
+            raise OSError("Unknown synthesis mode! {}".format(synth_mode))
+
         tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(build_name))
         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
         tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
@@ -205,6 +215,7 @@ class XilinxVivadoToolchain:
 
     def build(self, platform, fragment, build_dir="build", build_name="top",
             toolchain_path=None, source=True, run=True, **kwargs):
+        synth_mode = kwargs.get('synth_mode', 'yosys')
         if toolchain_path is None:
             if sys.platform == "win32":
                 toolchain_path = "C:\\Xilinx\\Vivado"
@@ -228,9 +239,13 @@ class XilinxVivadoToolchain:
         sources = platform.sources + [(v_file, "verilog", "work")]
         edifs = platform.edifs
         ips = platform.ips
-        self._build_batch(platform, sources, edifs, ips, build_name)
+        self._build_batch(platform, sources, edifs, ips, build_name, synth_mode=synth_mode)
         tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
         if run:
+            if synth_mode == "yosys":
+                common._run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
+            else:
+                raise OSError("Error!")
             _run_vivado(build_name, toolchain_path, source)
 
         os.chdir(cwd)