build.py: LOC clock generator components to limit breakage of the ISE shitware

diff --git a/build.py b/build.py
index 73bd7720b6c6049922203a5eb3b2233882bf460c..a87c8a3073d0a511723c99db96f3ee90919ee498 100755 (executable)
--- a/build.py
+++ b/build.py
@@ -18,6 +18,8 @@ TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
 """, clk50=platform.lookup_request("clk50"))
 
        platform.add_platform_command("""
+INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
+INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";