abc9: cleanup

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f6627602b47374b84dbb350f824d55cc9e2192f5..2af0676b119cdfe3b68cb5f088f4467e0341d2d2 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -26,9 +26,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
-                           // to one LUT6 (instead of a LUT5 + LUT2)
-
 struct Abc9Pass : public ScriptPass
 {
        Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { }
@@ -39,8 +36,9 @@ struct Abc9Pass : public ScriptPass
                log("\n");
                log("    abc9 [options] [selection]\n");
                log("\n");
-               log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
-               log("library to a target architecture. Only fully-selected modules are supported.\n");
+               log("This script pass performs a sequence of commands to facilitate the use of the ABC\n");
+               log("tool [1] for technology mapping of the current design to a target FPGA\n");
+               log("architecture. Only fully-selected modules are supported.\n");
                log("\n");
                log("    -exe <command>\n");
 #ifdef ABCEXTERNAL
@@ -59,21 +57,13 @@ struct Abc9Pass : public ScriptPass
                log("        replaced with blanks before the string is passed to ABC.\n");
                log("\n");
                log("        if no -script parameter is given, the following scripts are used:\n");
-               log("\n");
-               log("        for -lut/-luts (only one LUT size):\n");
-               // FIXME
-               //log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
-               log("\n");
-               log("        for -lut/-luts (different LUT sizes):\n");
-               // FIXME
+               //FIXME:
                //log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
                log("\n");
                log("    -fast\n");
                log("        use different default scripts that are slightly faster (at the cost\n");
                log("        of output quality):\n");
-               log("\n");
-               log("        for -lut/-luts:\n");
-               // FIXME
+               //FIXME:
                //log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
                log("\n");
                log("    -D <picoseconds>\n");

diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index f7dafda9690e4574c408f69a9f83f79b2d266adb..3108765a1005b536a2373d6aa2466c3d949deced 100644 (file)
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -289,10 +289,12 @@ struct Abc9ExePass : public Pass {
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
-               log("    abc9_exe [options] [selection]\n");
+               log("    abc9_exe [options]\n");
                log("\n");
-               log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
-               log("library to a target architecture.\n");
+               log(" \n");
+               log("This pass uses the ABC tool [1] for technology mapping of the top module\n");
+               log("(according to the (* top *) attribute or if only one module is currently selected)\n");
+               log("to a target FPGA architecture.\n");
                log("\n");
                log("    -exe <command>\n");
 #ifdef ABCEXTERNAL
@@ -311,18 +313,11 @@ struct Abc9ExePass : public Pass {
                log("        replaced with blanks before the string is passed to ABC.\n");
                log("\n");
                log("        if no -script parameter is given, the following scripts are used:\n");
-               log("\n");
-               log("        for -lut/-luts (only one LUT size):\n");
-               log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
-               log("\n");
-               log("        for -lut/-luts (different LUT sizes):\n");
                log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
                log("\n");
                log("    -fast\n");
                log("        use different default scripts that are slightly faster (at the cost\n");
                log("        of output quality):\n");
-               log("\n");
-               log("        for -lut/-luts:\n");
                log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
                log("\n");
                log("    -D <picoseconds>\n");

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 7c72087112d88ecc7c53db32046f21c286f42929..6f089447e47daa12154d7fddd00698874e094a9c 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -40,7 +40,7 @@ void break_scc(RTLIL::Module *module)
        //   its output ports into a new PO, and drive its previous
        //   sinks with a new PI
        pool<RTLIL::Const> ids_seen;
-       for (auto cell : module->selected_cells()) {
+       for (auto cell : module->cells()) {
                auto it = cell->attributes.find(ID(abc9_scc_id));
                if (it == cell->attributes.end())
                        continue;
@@ -116,7 +116,7 @@ void prep_dff(RTLIL::Module *module)
        typedef SigSpec clkdomain_t;
        dict<clkdomain_t, int> clk_to_mergeability;
 
-       for (auto cell : module->selected_cells()) {
+       for (auto cell : module->cells()) {
                if (cell->type != "$__ABC9_FF_")
                        continue;
 
@@ -179,11 +179,8 @@ void prep_dff(RTLIL::Module *module)
                                ++it;
                }
 
-               for (auto &conn : holes_module->connections_) {
-                       auto it = replace.find(conn);
-                       if (it != replace.end())
-                               conn = it->second;
-               }
+               for (auto &conn : holes_module->connections_)
+                       conn = replace.at(conn, conn);
        }
 }
 
@@ -198,7 +195,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
        TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
        bool abc9_box_seen = false;
 
-       for (auto cell : module->selected_cells()) {
+       for (auto cell : module->cells()) {
                if (cell->type == "$__ABC9_FF_")
                        continue;
 
@@ -236,21 +233,23 @@ void prep_holes(RTLIL::Module *module, bool dff)
                        for (auto user_cell : it.second)
                                toposort.edge(driver_cell, user_cell);
 
-#if 0
-       toposort.analyze_loops = true;
-#endif
+       if (ys_debug(1))
+               toposort.analyze_loops = true;
+
        bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
-#if 0
-       unsigned i = 0;
-       for (auto &it : toposort.loops) {
-               log("  loop %d\n", i++);
-               for (auto cell_name : it) {
-                       auto cell = module->cell(cell_name);
-                       log_assert(cell);
-                       log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
+
+       if (ys_debug(1)) {
+               unsigned i = 0;
+               for (auto &it : toposort.loops) {
+                       log("  loop %d\n", i++);
+                       for (auto cell_name : it) {
+                               auto cell = module->cell(cell_name);
+                               log_assert(cell);
+                               log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
+                       }
                }
        }
-#endif
+
        log_assert(no_loops);
 
        vector<Cell*> box_list;
@@ -845,6 +844,12 @@ struct Abc9OpsPass : public Pass {
                }
                extra_args(args, argidx, design);
 
+               if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode))
+                       log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
+
+               if (dff_mode && !prep_holes_mode)
+                       log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
+
                for (auto mod : design->selected_modules()) {
                        if (mod->get_bool_attribute("\\abc9_holes"))
                                continue;
@@ -854,6 +859,9 @@ struct Abc9OpsPass : public Pass {
                                continue;
                        }
 
+                       if (!design->selected_whole_module(mod))
+                               log_error("Can't handle partially selected module %s!\n", log_id(mod));
+
                        if (break_scc_mode)
                                break_scc(mod);
                        if (unbreak_scc_mode)